2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82945GM:
37 case PCI_DEVICE_ID_INTEL_82945P:
38 case PCI_DEVICE_ID_INTEL_82975X:
39 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
41 case PCI_DEVICE_ID_INTEL_PM965:
42 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
43 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
45 case 0x1234: // Dummy for non-existent functionality
46 printf("This northbrigde does not have EPBAR.\n");
49 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
53 epbar = map_physical(epbar_phys, size);
56 perror("Error mapping EPBAR");
60 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
61 for (i = 0; i < size; i += 4) {
62 if (*(uint32_t *)(epbar + i))
63 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
66 unmap_physical((void *)epbar, size);
71 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
73 int print_dmibar(struct pci_dev *nb)
75 int i, size = (4 * 1024);
76 volatile uint8_t *dmibar;
79 printf("\n============= DMIBAR ============\n\n");
81 switch (nb->device_id) {
82 case PCI_DEVICE_ID_INTEL_82945GM:
83 case PCI_DEVICE_ID_INTEL_82945P:
84 case PCI_DEVICE_ID_INTEL_82975X:
85 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
87 case PCI_DEVICE_ID_INTEL_PM965:
88 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
89 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
91 case 0x1234: // Dummy for non-existent functionality
92 printf("This northbrigde does not have DMIBAR.\n");
95 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
99 dmibar = map_physical(dmibar_phys, size);
101 if (dmibar == NULL) {
102 perror("Error mapping DMIBAR");
106 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
107 for (i = 0; i < size; i += 4) {
108 if (*(uint32_t *)(dmibar + i))
109 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
112 unmap_physical((void *)dmibar, size);
117 * PCIe MMIO configuration space
119 int print_pciexbar(struct pci_dev *nb)
121 uint64_t pciexbar_reg;
122 uint64_t pciexbar_phys;
123 volatile uint8_t *pciexbar;
124 int max_busses, devbase, i;
127 printf("========= PCIEXBAR ========\n\n");
129 switch (nb->device_id) {
130 case PCI_DEVICE_ID_INTEL_82945GM:
131 case PCI_DEVICE_ID_INTEL_82945P:
132 case PCI_DEVICE_ID_INTEL_82975X:
133 pciexbar_reg = pci_read_long(nb, 0x48);
135 case PCI_DEVICE_ID_INTEL_PM965:
136 pciexbar_reg = pci_read_long(nb, 0x60);
137 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
139 case 0x1234: // Dummy for non-existent functionality
140 printf("Error: This northbrigde does not have PCIEXBAR.\n");
143 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
147 if (!(pciexbar_reg & (1 << 0))) {
148 printf("PCIEXBAR register is disabled.\n");
152 switch ((pciexbar_reg >> 1) & 3) {
154 pciexbar_phys = pciexbar_reg & (0xff << 28);
158 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
162 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
166 printf("Undefined address base. Bailing out.\n");
170 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
172 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
174 if (pciexbar == NULL) {
175 perror("Error mapping PCIEXBAR");
179 for (bus = 0; bus < max_busses; bus++) {
180 for (dev = 0; dev < 32; dev++) {
181 for (fn = 0; fn < 8; fn++) {
182 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
184 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
187 /* This is a heuristics. Anyone got a better check? */
188 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
189 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
191 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
196 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
197 for (i = 0; i < 4096; i++) {
199 printf("\n%04x:", i);
200 printf(" %02x", *(pciexbar+devbase+i));
207 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));