2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82915:
37 case PCI_DEVICE_ID_INTEL_82945GM:
38 case PCI_DEVICE_ID_INTEL_82945GSE:
39 case PCI_DEVICE_ID_INTEL_82945P:
40 case PCI_DEVICE_ID_INTEL_82975X:
41 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
43 case PCI_DEVICE_ID_INTEL_PM965:
44 case PCI_DEVICE_ID_INTEL_Q965:
45 case PCI_DEVICE_ID_INTEL_82Q35:
46 case PCI_DEVICE_ID_INTEL_82G33:
47 case PCI_DEVICE_ID_INTEL_82Q33:
48 case PCI_DEVICE_ID_INTEL_X44:
49 case PCI_DEVICE_ID_INTEL_32X0:
50 case PCI_DEVICE_ID_INTEL_GS45:
51 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
52 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
53 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
54 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
56 case PCI_DEVICE_ID_INTEL_82810:
57 case PCI_DEVICE_ID_INTEL_82810DC:
58 case PCI_DEVICE_ID_INTEL_82810E_MC:
59 case PCI_DEVICE_ID_INTEL_82830M:
60 case PCI_DEVICE_ID_INTEL_82865:
61 printf("This northbridge does not have EPBAR.\n");
64 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
68 epbar = map_physical(epbar_phys, size);
71 perror("Error mapping EPBAR");
75 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
76 for (i = 0; i < size; i += 4) {
77 if (*(uint32_t *)(epbar + i))
78 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
81 unmap_physical((void *)epbar, size);
86 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
88 int print_dmibar(struct pci_dev *nb)
90 int i, size = (4 * 1024);
91 volatile uint8_t *dmibar;
94 printf("\n============= DMIBAR ============\n\n");
96 switch (nb->device_id) {
97 case PCI_DEVICE_ID_INTEL_82915:
98 case PCI_DEVICE_ID_INTEL_82945GM:
99 case PCI_DEVICE_ID_INTEL_82945GSE:
100 case PCI_DEVICE_ID_INTEL_82945P:
101 case PCI_DEVICE_ID_INTEL_82975X:
102 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
104 case PCI_DEVICE_ID_INTEL_PM965:
105 case PCI_DEVICE_ID_INTEL_Q965:
106 case PCI_DEVICE_ID_INTEL_82Q35:
107 case PCI_DEVICE_ID_INTEL_82G33:
108 case PCI_DEVICE_ID_INTEL_82Q33:
109 case PCI_DEVICE_ID_INTEL_X44:
110 case PCI_DEVICE_ID_INTEL_32X0:
111 case PCI_DEVICE_ID_INTEL_GS45:
112 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
113 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
114 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
115 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
117 case PCI_DEVICE_ID_INTEL_82810:
118 case PCI_DEVICE_ID_INTEL_82810DC:
119 case PCI_DEVICE_ID_INTEL_82810E_MC:
120 case PCI_DEVICE_ID_INTEL_82865:
121 printf("This northbridge does not have DMIBAR.\n");
123 case PCI_DEVICE_ID_INTEL_X58:
124 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
127 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
131 dmibar = map_physical(dmibar_phys, size);
133 if (dmibar == NULL) {
134 perror("Error mapping DMIBAR");
138 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
139 for (i = 0; i < size; i += 4) {
140 if (*(uint32_t *)(dmibar + i))
141 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
144 unmap_physical((void *)dmibar, size);
149 * PCIe MMIO configuration space
151 int print_pciexbar(struct pci_dev *nb)
153 uint64_t pciexbar_reg;
154 uint64_t pciexbar_phys;
155 volatile uint8_t *pciexbar;
156 int max_busses, devbase, i;
159 printf("========= PCIEXBAR ========\n\n");
161 switch (nb->device_id) {
162 case PCI_DEVICE_ID_INTEL_82915:
163 case PCI_DEVICE_ID_INTEL_82945GM:
164 case PCI_DEVICE_ID_INTEL_82945GSE:
165 case PCI_DEVICE_ID_INTEL_82945P:
166 case PCI_DEVICE_ID_INTEL_82975X:
167 pciexbar_reg = pci_read_long(nb, 0x48);
169 case PCI_DEVICE_ID_INTEL_PM965:
170 case PCI_DEVICE_ID_INTEL_Q965:
171 case PCI_DEVICE_ID_INTEL_82Q35:
172 case PCI_DEVICE_ID_INTEL_82G33:
173 case PCI_DEVICE_ID_INTEL_82Q33:
174 case PCI_DEVICE_ID_INTEL_X44:
175 case PCI_DEVICE_ID_INTEL_32X0:
176 case PCI_DEVICE_ID_INTEL_GS45:
177 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
178 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
179 pciexbar_reg = pci_read_long(nb, 0x60);
180 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
182 case PCI_DEVICE_ID_INTEL_82810:
183 case PCI_DEVICE_ID_INTEL_82810DC:
184 case PCI_DEVICE_ID_INTEL_82810E_MC:
185 case PCI_DEVICE_ID_INTEL_82865:
186 printf("Error: This northbridge does not have PCIEXBAR.\n");
189 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
193 if (!(pciexbar_reg & (1 << 0))) {
194 printf("PCIEXBAR register is disabled.\n");
198 switch ((pciexbar_reg >> 1) & 3) {
200 pciexbar_phys = pciexbar_reg & (0xff << 28);
204 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
208 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
212 printf("Undefined address base. Bailing out.\n");
216 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
218 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
220 if (pciexbar == NULL) {
221 perror("Error mapping PCIEXBAR");
225 for (bus = 0; bus < max_busses; bus++) {
226 for (dev = 0; dev < 32; dev++) {
227 for (fn = 0; fn < 8; fn++) {
228 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
230 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
233 /* This is a heuristics. Anyone got a better check? */
234 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
235 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
237 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
242 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
243 for (i = 0; i < 4096; i++) {
245 printf("\n%04x:", i);
246 printf(" %02x", *(pciexbar+devbase+i));
253 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));