2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82915:
37 case PCI_DEVICE_ID_INTEL_82945GM:
38 case PCI_DEVICE_ID_INTEL_82945GSE:
39 case PCI_DEVICE_ID_INTEL_82945P:
40 case PCI_DEVICE_ID_INTEL_82975X:
41 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
43 case PCI_DEVICE_ID_INTEL_PM965:
44 case PCI_DEVICE_ID_INTEL_Q965:
45 case PCI_DEVICE_ID_INTEL_82Q35:
46 case PCI_DEVICE_ID_INTEL_82G33:
47 case PCI_DEVICE_ID_INTEL_82Q33:
48 case PCI_DEVICE_ID_INTEL_GS45:
49 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
50 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
51 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
52 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
54 case PCI_DEVICE_ID_INTEL_82810:
55 case PCI_DEVICE_ID_INTEL_82810DC:
56 case PCI_DEVICE_ID_INTEL_82810E_MC:
57 case PCI_DEVICE_ID_INTEL_82830M:
58 case PCI_DEVICE_ID_INTEL_82865:
59 printf("This northbridge does not have EPBAR.\n");
62 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
66 epbar = map_physical(epbar_phys, size);
69 perror("Error mapping EPBAR");
73 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
74 for (i = 0; i < size; i += 4) {
75 if (*(uint32_t *)(epbar + i))
76 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
79 unmap_physical((void *)epbar, size);
84 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
86 int print_dmibar(struct pci_dev *nb)
88 int i, size = (4 * 1024);
89 volatile uint8_t *dmibar;
92 printf("\n============= DMIBAR ============\n\n");
94 switch (nb->device_id) {
95 case PCI_DEVICE_ID_INTEL_82915:
96 case PCI_DEVICE_ID_INTEL_82945GM:
97 case PCI_DEVICE_ID_INTEL_82945GSE:
98 case PCI_DEVICE_ID_INTEL_82945P:
99 case PCI_DEVICE_ID_INTEL_82975X:
100 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
102 case PCI_DEVICE_ID_INTEL_PM965:
103 case PCI_DEVICE_ID_INTEL_Q965:
104 case PCI_DEVICE_ID_INTEL_82Q35:
105 case PCI_DEVICE_ID_INTEL_82G33:
106 case PCI_DEVICE_ID_INTEL_82Q33:
107 case PCI_DEVICE_ID_INTEL_GS45:
108 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
109 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
110 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
111 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
113 case PCI_DEVICE_ID_INTEL_82810:
114 case PCI_DEVICE_ID_INTEL_82810DC:
115 case PCI_DEVICE_ID_INTEL_82810E_MC:
116 case PCI_DEVICE_ID_INTEL_82865:
117 printf("This northbridge does not have DMIBAR.\n");
119 case PCI_DEVICE_ID_INTEL_X58:
120 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
123 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
127 dmibar = map_physical(dmibar_phys, size);
129 if (dmibar == NULL) {
130 perror("Error mapping DMIBAR");
134 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
135 for (i = 0; i < size; i += 4) {
136 if (*(uint32_t *)(dmibar + i))
137 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
140 unmap_physical((void *)dmibar, size);
145 * PCIe MMIO configuration space
147 int print_pciexbar(struct pci_dev *nb)
149 uint64_t pciexbar_reg;
150 uint64_t pciexbar_phys;
151 volatile uint8_t *pciexbar;
152 int max_busses, devbase, i;
155 printf("========= PCIEXBAR ========\n\n");
157 switch (nb->device_id) {
158 case PCI_DEVICE_ID_INTEL_82915:
159 case PCI_DEVICE_ID_INTEL_82945GM:
160 case PCI_DEVICE_ID_INTEL_82945GSE:
161 case PCI_DEVICE_ID_INTEL_82945P:
162 case PCI_DEVICE_ID_INTEL_82975X:
163 pciexbar_reg = pci_read_long(nb, 0x48);
165 case PCI_DEVICE_ID_INTEL_PM965:
166 case PCI_DEVICE_ID_INTEL_Q965:
167 case PCI_DEVICE_ID_INTEL_82Q35:
168 case PCI_DEVICE_ID_INTEL_82G33:
169 case PCI_DEVICE_ID_INTEL_82Q33:
170 case PCI_DEVICE_ID_INTEL_GS45:
171 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
172 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
173 pciexbar_reg = pci_read_long(nb, 0x60);
174 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
176 case PCI_DEVICE_ID_INTEL_82810:
177 case PCI_DEVICE_ID_INTEL_82810DC:
178 case PCI_DEVICE_ID_INTEL_82810E_MC:
179 case PCI_DEVICE_ID_INTEL_82865:
180 printf("Error: This northbridge does not have PCIEXBAR.\n");
183 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
187 if (!(pciexbar_reg & (1 << 0))) {
188 printf("PCIEXBAR register is disabled.\n");
192 switch ((pciexbar_reg >> 1) & 3) {
194 pciexbar_phys = pciexbar_reg & (0xff << 28);
198 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
202 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
206 printf("Undefined address base. Bailing out.\n");
210 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
212 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
214 if (pciexbar == NULL) {
215 perror("Error mapping PCIEXBAR");
219 for (bus = 0; bus < max_busses; bus++) {
220 for (dev = 0; dev < 32; dev++) {
221 for (fn = 0; fn < 8; fn++) {
222 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
224 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
227 /* This is a heuristics. Anyone got a better check? */
228 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
229 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
231 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
236 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
237 for (i = 0; i < 4096; i++) {
239 printf("\n%04x:", i);
240 printf(" %02x", *(pciexbar+devbase+i));
247 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));