util/inteltool/inteltool.c

   1 /*
   2  * inteltool - dump all registers on an Intel CPU + chipset based system.
   3  *
   4  * Copyright (C) 2008-2010 by coresystems GmbH
   5  *  written by Stefan Reinauer <stepan@coresystems.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <stdio.h>
  22 #include <stdlib.h>
  23 #include <getopt.h>
  24 #include <fcntl.h>
  25 #include <sys/mman.h>
  26 #include "inteltool.h"
  27
  28 static const struct {
  29         uint16_t vendor_id, device_id;
  30         char *name;
  31 } supported_chips_list[] = {
  32         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
  33         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
  34         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
  35         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
  36         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
  37         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
  38         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
  39         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
  40         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
  41         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
  42         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
  43         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
  44         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
  45         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
  46         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
  47         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
  48         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
  49         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
  50         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
  51         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
  52         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
  53         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
  54         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
  55         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
  56         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
  57         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
  58         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
  59         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
  60         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
  61         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
  62         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
  63         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
  64         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
  65         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
  66         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
  67         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
  68         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
  69         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
  70 };
  71
  72 #ifndef __DARWIN__
  73 static int fd_mem;
  74
  75 void *map_physical(unsigned long phys_addr, size_t len)
  76 {
  77         void *virt_addr;
  78
  79         virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
  80                     fd_mem, (off_t) phys_addr);
  81
  82         if (virt_addr == MAP_FAILED) {
  83                 printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len);
  84                 return NULL;
  85         }
  86
  87         return virt_addr;
  88 }
  89
  90 void unmap_physical(void *virt_addr, size_t len)
  91 {
  92         munmap(virt_addr, len);
  93 }
  94 #endif
  95
  96 void print_version(void)
  97 {
  98         printf("inteltool v%s -- ", INTELTOOL_VERSION);
  99         printf("Copyright (C) 2008 coresystems GmbH\n\n");
 100         printf(
 101     "This program is free software: you can redistribute it and/or modify\n"
 102     "it under the terms of the GNU General Public License as published by\n"
 103     "the Free Software Foundation, version 2 of the License.\n\n"
 104     "This program is distributed in the hope that it will be useful,\n"
 105     "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
 106     "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
 107     "GNU General Public License for more details.\n\n"
 108     "You should have received a copy of the GNU General Public License\n"
 109     "along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n");
 110 }
 111
 112 void print_usage(const char *name)
 113 {
 114         printf("usage: %s [-vh?grpmedPMa]\n", name);
 115         printf("\n"
 116              "   -v | --version:                   print the version\n"
 117              "   -h | --help:                      print this help\n\n"
 118              "   -g | --gpio:                      dump soutbridge GPIO registers\n"
 119              "   -r | --rcba:                      dump soutbridge RCBA registers\n"
 120              "   -p | --pmbase:                    dump soutbridge Power Management registers\n\n"
 121              "   -m | --mchbar:                    dump northbridge Memory Controller registers\n"
 122              "   -e | --epbar:                     dump northbridge EPBAR registers\n"
 123              "   -d | --dmibar:                    dump northbridge DMIBAR registers\n"
 124              "   -P | --pciexpress:                dump northbridge PCIEXBAR registers\n\n"
 125              "   -M | --msrs:                      dump CPU MSRs\n"
 126              "   -a | --all:                       dump all known registers\n"
 127              "\n");
 128         exit(1);
 129 }
 130
 131 int main(int argc, char *argv[])
 132 {
 133         struct pci_access *pacc;
 134         struct pci_dev *sb = NULL, *nb, *dev;
 135         int i, opt, option_index = 0;
 136         unsigned int id;
 137
 138         char *sbname = "unknown", *nbname = "unknown";
 139
 140         int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
 141         int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
 142         int dump_pciexbar = 0, dump_coremsrs = 0;
 143
 144         static struct option long_options[] = {
 145                 {"version", 0, 0, 'v'},
 146                 {"help", 0, 0, 'h'},
 147                 {"gpios", 0, 0, 'g'},
 148                 {"mchbar", 0, 0, 'm'},
 149                 {"rcba", 0, 0, 'r'},
 150                 {"pmbase", 0, 0, 'p'},
 151                 {"epbar", 0, 0, 'e'},
 152                 {"dmibar", 0, 0, 'd'},
 153                 {"pciexpress", 0, 0, 'P'},
 154                 {"msrs", 0, 0, 'M'},
 155                 {"all", 0, 0, 'a'},
 156                 {0, 0, 0, 0}
 157         };
 158
 159         while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
 160                                   long_options, &option_index)) != EOF) {
 161                 switch (opt) {
 162                 case 'v':
 163                         print_version();
 164                         exit(0);
 165                         break;
 166                 case 'g':
 167                         dump_gpios = 1;
 168                         break;
 169                 case 'm':
 170                         dump_mchbar = 1;
 171                         break;
 172                 case 'r':
 173                         dump_rcba = 1;
 174                         break;
 175                 case 'p':
 176                         dump_pmbase = 1;
 177                         break;
 178                 case 'e':
 179                         dump_epbar = 1;
 180                         break;
 181                 case 'd':
 182                         dump_dmibar = 1;
 183                         break;
 184                 case 'P':
 185                         dump_pciexbar = 1;
 186                         break;
 187                 case 'M':
 188                         dump_coremsrs = 1;
 189                         break;
 190                 case 'a':
 191                         dump_gpios = 1;
 192                         dump_mchbar = 1;
 193                         dump_rcba = 1;
 194                         dump_pmbase = 1;
 195                         dump_epbar = 1;
 196                         dump_dmibar = 1;
 197                         dump_pciexbar = 1;
 198                         dump_coremsrs = 1;
 199                         break;
 200                 case 'h':
 201                 case '?':
 202                 default:
 203                         print_usage(argv[0]);
 204                         exit(0);
 205                         break;
 206                 }
 207         }
 208
 209         if (iopl(3)) {
 210                 printf("You need to be root.\n");
 211                 exit(1);
 212         }
 213
 214 #ifndef __DARWIN__
 215         if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
 216                 perror("Can not open /dev/mem");
 217                 exit(1);
 218         }
 219 #endif
 220
 221         pacc = pci_alloc();
 222         pci_init(pacc);
 223         pci_scan_bus(pacc);
 224
 225         /* Find the required devices */
 226         for (dev = pacc->devices; dev; dev = dev->next) {
 227                 pci_fill_info(dev, PCI_FILL_CLASS);
 228                 /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
 229                 if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
 230                         if (sb == NULL)
 231                                 sb = dev;
 232                         else
 233                                 fprintf(stderr, "Multiple devices with class ID"
 234                                         " 0x0601, using %02x%02x:%02x.%02x\n",
 235                                         dev->domain, dev->bus, dev->dev,
 236                                         dev->func);
 237                 }
 238         }
 239
 240         if (!sb) {
 241                 printf("No southbridge found.\n");
 242                 exit(1);
 243         }
 244
 245         pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
 246
 247         if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
 248                 printf("Not an Intel(R) southbridge.\n");
 249                 exit(1);
 250         }
 251
 252         nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
 253         if (!nb) {
 254                 printf("No northbridge found.\n");
 255                 exit(1);
 256         }
 257
 258         pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
 259
 260         if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
 261                 printf("Not an Intel(R) northbridge.\n");
 262                 exit(1);
 263         }
 264
 265         id = cpuid(1);
 266
 267         /* Intel has suggested applications to display the family of a CPU as
 268          * the sum of the "Family" and the "Extended Family" fields shown
 269          * above, and the model as the sum of the "Model" and the 4-bit
 270          * left-shifted "Extended Model" fields.
 271          * http://download.intel.com/design/processor/applnots/24161832.pdf
 272          */
 273         printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
 274                         (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
 275                         ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
 276
 277         /* Determine names */
 278         for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
 279                 if (nb->device_id == supported_chips_list[i].device_id)
 280                         nbname = supported_chips_list[i].name;
 281         for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
 282                 if (sb->device_id == supported_chips_list[i].device_id)
 283                         sbname = supported_chips_list[i].name;
 284
 285         printf("Intel Northbridge: %04x:%04x (%s)\n",
 286                 nb->vendor_id, nb->device_id, nbname);
 287
 288         printf("Intel Southbridge: %04x:%04x (%s)\n",
 289                 sb->vendor_id, sb->device_id, sbname);
 290
 291         /* Now do the deed */
 292
 293         if (dump_gpios) {
 294                 print_gpios(sb);
 295                 printf("\n\n");
 296         }
 297
 298         if (dump_rcba) {
 299                 print_rcba(sb);
 300                 printf("\n\n");
 301         }
 302
 303         if (dump_pmbase) {
 304                 print_pmbase(sb);
 305                 printf("\n\n");
 306         }
 307
 308         if (dump_mchbar) {
 309                 print_mchbar(nb);
 310                 printf("\n\n");
 311         }
 312
 313         if (dump_epbar) {
 314                 print_epbar(nb);
 315                 printf("\n\n");
 316         }
 317
 318         if (dump_dmibar) {
 319                 print_dmibar(nb);
 320                 printf("\n\n");
 321         }
 322
 323         if (dump_pciexbar) {
 324                 print_pciexbar(nb);
 325                 printf("\n\n");
 326         }
 327
 328         if (dump_coremsrs) {
 329                 print_intel_core_msrs();
 330                 printf("\n\n");
 331         }
 332
 333         /* Clean up */
 334         pci_free_dev(nb);
 335         // pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
 336         pci_cleanup(pacc);
 337
 338         return 0;
 339 }