2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
5 * written by Stefan Reinauer <stepan@coresystems.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include "inteltool.h"
29 uint16_t vendor_id, device_id;
31 } supported_chips_list[] = {
32 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
33 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
34 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
35 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
36 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
37 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
38 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
39 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
40 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
41 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
42 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
43 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" },
44 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
45 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
46 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
47 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
48 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
49 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
50 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
51 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
52 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
53 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
54 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
55 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
56 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
57 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
58 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
59 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
60 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
61 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
62 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
63 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
64 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
65 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
66 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
67 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
68 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
69 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
70 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
71 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
72 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
73 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
74 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
80 void *map_physical(unsigned long phys_addr, size_t len)
84 virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
85 fd_mem, (off_t) phys_addr);
87 if (virt_addr == MAP_FAILED) {
88 printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len);
95 void unmap_physical(void *virt_addr, size_t len)
97 munmap(virt_addr, len);
101 void print_version(void)
103 printf("inteltool v%s -- ", INTELTOOL_VERSION);
104 printf("Copyright (C) 2008 coresystems GmbH\n\n");
106 "This program is free software: you can redistribute it and/or modify\n"
107 "it under the terms of the GNU General Public License as published by\n"
108 "the Free Software Foundation, version 2 of the License.\n\n"
109 "This program is distributed in the hope that it will be useful,\n"
110 "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
111 "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
112 "GNU General Public License for more details.\n\n"
113 "You should have received a copy of the GNU General Public License\n"
114 "along with this program. If not, see <http://www.gnu.org/licenses/>.\n\n");
117 void print_usage(const char *name)
119 printf("usage: %s [-vh?grpmedPMa]\n", name);
121 " -v | --version: print the version\n"
122 " -h | --help: print this help\n\n"
123 " -g | --gpio: dump soutbridge GPIO registers\n"
124 " -r | --rcba: dump soutbridge RCBA registers\n"
125 " -p | --pmbase: dump soutbridge Power Management registers\n\n"
126 " -m | --mchbar: dump northbridge Memory Controller registers\n"
127 " -e | --epbar: dump northbridge EPBAR registers\n"
128 " -d | --dmibar: dump northbridge DMIBAR registers\n"
129 " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n"
130 " -M | --msrs: dump CPU MSRs\n"
131 " -a | --all: dump all known registers\n"
136 int main(int argc, char *argv[])
138 struct pci_access *pacc;
139 struct pci_dev *sb = NULL, *nb, *dev;
140 int i, opt, option_index = 0;
143 char *sbname = "unknown", *nbname = "unknown";
145 int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
146 int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
147 int dump_pciexbar = 0, dump_coremsrs = 0;
149 static struct option long_options[] = {
150 {"version", 0, 0, 'v'},
152 {"gpios", 0, 0, 'g'},
153 {"mchbar", 0, 0, 'm'},
155 {"pmbase", 0, 0, 'p'},
156 {"epbar", 0, 0, 'e'},
157 {"dmibar", 0, 0, 'd'},
158 {"pciexpress", 0, 0, 'P'},
164 while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
165 long_options, &option_index)) != EOF) {
208 print_usage(argv[0]);
215 printf("You need to be root.\n");
220 if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
221 perror("Can not open /dev/mem");
230 /* Find the required devices */
231 for (dev = pacc->devices; dev; dev = dev->next) {
232 pci_fill_info(dev, PCI_FILL_CLASS);
233 /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
234 if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
238 fprintf(stderr, "Multiple devices with class ID"
239 " 0x0601, using %02x%02x:%02x.%02x\n",
240 dev->domain, dev->bus, dev->dev,
246 printf("No southbridge found.\n");
250 pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
252 if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
253 printf("Not an Intel(R) southbridge.\n");
257 nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
259 printf("No northbridge found.\n");
263 pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
265 if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
266 printf("Not an Intel(R) northbridge.\n");
272 /* Intel has suggested applications to display the family of a CPU as
273 * the sum of the "Family" and the "Extended Family" fields shown
274 * above, and the model as the sum of the "Model" and the 4-bit
275 * left-shifted "Extended Model" fields.
276 * http://download.intel.com/design/processor/applnots/24161832.pdf
278 printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
279 (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
280 ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
282 /* Determine names */
283 for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
284 if (nb->device_id == supported_chips_list[i].device_id)
285 nbname = supported_chips_list[i].name;
286 for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
287 if (sb->device_id == supported_chips_list[i].device_id)
288 sbname = supported_chips_list[i].name;
290 printf("Intel Northbridge: %04x:%04x (%s)\n",
291 nb->vendor_id, nb->device_id, nbname);
293 printf("Intel Southbridge: %04x:%04x (%s)\n",
294 sb->vendor_id, sb->device_id, sbname);
296 /* Now do the deed */
334 print_intel_core_msrs();
340 // pci_free_dev(sb); // TODO: glibc detected "double free or corruption"