util/inteltool/inteltool.c

   1 /*
   2  * inteltool - dump all registers on an Intel CPU + chipset based system.
   3  *
   4  * Copyright (C) 2008-2010 by coresystems GmbH
   5  *  written by Stefan Reinauer <stepan@coresystems.de>
   6  * Copyright (C) 2009 Carl-Daniel Hailfinger
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <stdio.h>
  23 #include <stdlib.h>
  24 #include <getopt.h>
  25 #include <fcntl.h>
  26 #include <sys/mman.h>
  27 #include "inteltool.h"
  28 #if defined(__FreeBSD__)
  29 #include <unistd.h>
  30 #endif
  31
  32 static const struct {
  33         uint16_t vendor_id, device_id;
  34         char *name;
  35 } supported_chips_list[] = {
  36         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
  37         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
  38         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
  39         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
  40         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
  41         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
  42         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
  43         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
  44         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" },
  45         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
  46         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
  47         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
  48         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" },
  49         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
  50         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
  51         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
  52         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
  53         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
  54         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
  55         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
  56         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
  57         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
  58         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
  59         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
  60         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
  61         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
  62         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
  63         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
  64         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
  65         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
  66         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
  67         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
  68         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
  69         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
  70         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
  71         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
  72         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
  73         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
  74         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
  75         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
  76         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" },
  77         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
  78         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
  79         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
  80         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
  81         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
  82         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
  83         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
  84         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
  85 };
  86
  87 #ifndef __DARWIN__
  88 static int fd_mem;
  89
  90 void *map_physical(uint64_t phys_addr, size_t len)
  91 {
  92         void *virt_addr;
  93
  94         virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
  95                     fd_mem, (off_t) phys_addr);
  96
  97         if (virt_addr == MAP_FAILED) {
  98                 printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len);
  99                 return NULL;
 100         }
 101
 102         return virt_addr;
 103 }
 104
 105 void unmap_physical(void *virt_addr, size_t len)
 106 {
 107         munmap(virt_addr, len);
 108 }
 109 #endif
 110
 111 void print_version(void)
 112 {
 113         printf("inteltool v%s -- ", INTELTOOL_VERSION);
 114         printf("Copyright (C) 2008 coresystems GmbH\n\n");
 115         printf(
 116     "This program is free software: you can redistribute it and/or modify\n"
 117     "it under the terms of the GNU General Public License as published by\n"
 118     "the Free Software Foundation, version 2 of the License.\n\n"
 119     "This program is distributed in the hope that it will be useful,\n"
 120     "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
 121     "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
 122     "GNU General Public License for more details.\n\n"
 123     "You should have received a copy of the GNU General Public License\n"
 124     "along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n");
 125 }
 126
 127 void print_usage(const char *name)
 128 {
 129         printf("usage: %s [-vh?grpmedPMa]\n", name);
 130         printf("\n"
 131              "   -v | --version:                   print the version\n"
 132              "   -h | --help:                      print this help\n\n"
 133              "   -g | --gpio:                      dump soutbridge GPIO registers\n"
 134              "   -r | --rcba:                      dump soutbridge RCBA registers\n"
 135              "   -p | --pmbase:                    dump soutbridge Power Management registers\n\n"
 136              "   -m | --mchbar:                    dump northbridge Memory Controller registers\n"
 137              "   -e | --epbar:                     dump northbridge EPBAR registers\n"
 138              "   -d | --dmibar:                    dump northbridge DMIBAR registers\n"
 139              "   -P | --pciexpress:                dump northbridge PCIEXBAR registers\n\n"
 140              "   -M | --msrs:                      dump CPU MSRs\n"
 141              "   -a | --all:                       dump all known registers\n"
 142              "\n");
 143         exit(1);
 144 }
 145
 146 int main(int argc, char *argv[])
 147 {
 148         struct pci_access *pacc;
 149         struct pci_dev *sb = NULL, *nb, *dev;
 150         int i, opt, option_index = 0;
 151         unsigned int id;
 152
 153         char *sbname = "unknown", *nbname = "unknown";
 154
 155         int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
 156         int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
 157         int dump_pciexbar = 0, dump_coremsrs = 0;
 158
 159         static struct option long_options[] = {
 160                 {"version", 0, 0, 'v'},
 161                 {"help", 0, 0, 'h'},
 162                 {"gpios", 0, 0, 'g'},
 163                 {"mchbar", 0, 0, 'm'},
 164                 {"rcba", 0, 0, 'r'},
 165                 {"pmbase", 0, 0, 'p'},
 166                 {"epbar", 0, 0, 'e'},
 167                 {"dmibar", 0, 0, 'd'},
 168                 {"pciexpress", 0, 0, 'P'},
 169                 {"msrs", 0, 0, 'M'},
 170                 {"all", 0, 0, 'a'},
 171                 {0, 0, 0, 0}
 172         };
 173
 174         while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
 175                                   long_options, &option_index)) != EOF) {
 176                 switch (opt) {
 177                 case 'v':
 178                         print_version();
 179                         exit(0);
 180                         break;
 181                 case 'g':
 182                         dump_gpios = 1;
 183                         break;
 184                 case 'm':
 185                         dump_mchbar = 1;
 186                         break;
 187                 case 'r':
 188                         dump_rcba = 1;
 189                         break;
 190                 case 'p':
 191                         dump_pmbase = 1;
 192                         break;
 193                 case 'e':
 194                         dump_epbar = 1;
 195                         break;
 196                 case 'd':
 197                         dump_dmibar = 1;
 198                         break;
 199                 case 'P':
 200                         dump_pciexbar = 1;
 201                         break;
 202                 case 'M':
 203                         dump_coremsrs = 1;
 204                         break;
 205                 case 'a':
 206                         dump_gpios = 1;
 207                         dump_mchbar = 1;
 208                         dump_rcba = 1;
 209                         dump_pmbase = 1;
 210                         dump_epbar = 1;
 211                         dump_dmibar = 1;
 212                         dump_pciexbar = 1;
 213                         dump_coremsrs = 1;
 214                         break;
 215                 case 'h':
 216                 case '?':
 217                 default:
 218                         print_usage(argv[0]);
 219                         exit(0);
 220                         break;
 221                 }
 222         }
 223
 224 #if defined(__FreeBSD__)
 225         int io_fd;
 226 #endif
 227
 228 #if defined(__FreeBSD__)
 229         if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
 230                 perror("/dev/io");
 231 #else
 232         if (iopl(3)) {
 233                 perror("iopl");
 234 #endif
 235                 printf("You need to be root.\n");
 236                 exit(1);
 237         }
 238
 239 #ifndef __DARWIN__
 240         if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
 241                 perror("Can not open /dev/mem");
 242                 exit(1);
 243         }
 244 #endif
 245
 246         pacc = pci_alloc();
 247         pci_init(pacc);
 248         pci_scan_bus(pacc);
 249
 250         /* Find the required devices */
 251         for (dev = pacc->devices; dev; dev = dev->next) {
 252                 pci_fill_info(dev, PCI_FILL_CLASS);
 253                 /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
 254                 if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
 255                         if (sb == NULL)
 256                                 sb = dev;
 257                         else
 258                                 fprintf(stderr, "Multiple devices with class ID"
 259                                         " 0x0601, using %02x%02x:%02x.%02x\n",
 260                                         dev->domain, dev->bus, dev->dev,
 261                                         dev->func);
 262                 }
 263         }
 264
 265         if (!sb) {
 266                 printf("No southbridge found.\n");
 267                 exit(1);
 268         }
 269
 270         pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
 271
 272         if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
 273                 printf("Not an Intel(R) southbridge.\n");
 274                 exit(1);
 275         }
 276
 277         nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
 278         if (!nb) {
 279                 printf("No northbridge found.\n");
 280                 exit(1);
 281         }
 282
 283         pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
 284
 285         if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
 286                 printf("Not an Intel(R) northbridge.\n");
 287                 exit(1);
 288         }
 289
 290         id = cpuid(1);
 291
 292         /* Intel has suggested applications to display the family of a CPU as
 293          * the sum of the "Family" and the "Extended Family" fields shown
 294          * above, and the model as the sum of the "Model" and the 4-bit
 295          * left-shifted "Extended Model" fields.
 296          * http://download.intel.com/design/processor/applnots/24161832.pdf
 297          */
 298         printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
 299                         (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
 300                         ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
 301
 302         /* Determine names */
 303         for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
 304                 if (nb->device_id == supported_chips_list[i].device_id)
 305                         nbname = supported_chips_list[i].name;
 306         for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
 307                 if (sb->device_id == supported_chips_list[i].device_id)
 308                         sbname = supported_chips_list[i].name;
 309
 310         printf("Intel Northbridge: %04x:%04x (%s)\n",
 311                 nb->vendor_id, nb->device_id, nbname);
 312
 313         printf("Intel Southbridge: %04x:%04x (%s)\n",
 314                 sb->vendor_id, sb->device_id, sbname);
 315
 316         /* Now do the deed */
 317
 318         if (dump_gpios) {
 319                 print_gpios(sb);
 320                 printf("\n\n");
 321         }
 322
 323         if (dump_rcba) {
 324                 print_rcba(sb);
 325                 printf("\n\n");
 326         }
 327
 328         if (dump_pmbase) {
 329                 print_pmbase(sb, pacc);
 330                 printf("\n\n");
 331         }
 332
 333         if (dump_mchbar) {
 334                 print_mchbar(nb, pacc);
 335                 printf("\n\n");
 336         }
 337
 338         if (dump_epbar) {
 339                 print_epbar(nb);
 340                 printf("\n\n");
 341         }
 342
 343         if (dump_dmibar) {
 344                 print_dmibar(nb);
 345                 printf("\n\n");
 346         }
 347
 348         if (dump_pciexbar) {
 349                 print_pciexbar(nb);
 350                 printf("\n\n");
 351         }
 352
 353         if (dump_coremsrs) {
 354                 print_intel_core_msrs();
 355                 printf("\n\n");
 356         }
 357
 358         /* Clean up */
 359         pci_free_dev(nb);
 360         // pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
 361         pci_cleanup(pacc);
 362
 363         return 0;
 364 }