inteltool: Add Intel i63xx I/O Controller Hub
[coreboot.git] / util / inteltool / inteltool.c
1 /*
2  * inteltool - dump all registers on an Intel CPU + chipset based system.
3  *
4  * Copyright (C) 2008-2010 by coresystems GmbH
5  *  written by Stefan Reinauer <stepan@coresystems.de>
6  * Copyright (C) 2009 Carl-Daniel Hailfinger
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include <getopt.h>
25 #include <fcntl.h>
26 #include <sys/mman.h>
27 #include "inteltool.h"
28 #if defined(__FreeBSD__)
29 #include <unistd.h>
30 #endif
31
32 static const struct {
33         uint16_t vendor_id, device_id;
34         char *name;
35 } supported_chips_list[] = {
36         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
37         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
38         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
39         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
40         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
41         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
42         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
43         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
44         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" },
45         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
46         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
47         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
48         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" },
49         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
50         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
51         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
52         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
53         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
54         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
55         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
56         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
57         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
58         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
59         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
60         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
61         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
62         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
63         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
64         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
65         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
66         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
67         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
68         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
69         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
70         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
71         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
72         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
73         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
74         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
75         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
76         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" },
77         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
78         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
79         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
80         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
81         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
82         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
83         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
84         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
85         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" },
86 };
87
88 #ifndef __DARWIN__
89 static int fd_mem;
90
91 void *map_physical(uint64_t phys_addr, size_t len)
92 {
93         void *virt_addr;
94
95         virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
96                     fd_mem, (off_t) phys_addr);
97
98         if (virt_addr == MAP_FAILED) {
99                 printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len);
100                 return NULL;
101         }
102
103         return virt_addr;
104 }
105
106 void unmap_physical(void *virt_addr, size_t len)
107 {
108         munmap(virt_addr, len);
109 }
110 #endif
111
112 void print_version(void)
113 {
114         printf("inteltool v%s -- ", INTELTOOL_VERSION);
115         printf("Copyright (C) 2008 coresystems GmbH\n\n");
116         printf(
117     "This program is free software: you can redistribute it and/or modify\n"
118     "it under the terms of the GNU General Public License as published by\n"
119     "the Free Software Foundation, version 2 of the License.\n\n"
120     "This program is distributed in the hope that it will be useful,\n"
121     "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
122     "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
123     "GNU General Public License for more details.\n\n"
124     "You should have received a copy of the GNU General Public License\n"
125     "along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n");
126 }
127
128 void print_usage(const char *name)
129 {
130         printf("usage: %s [-vh?grpmedPMa]\n", name);
131         printf("\n"
132              "   -v | --version:                   print the version\n"
133              "   -h | --help:                      print this help\n\n"
134              "   -g | --gpio:                      dump soutbridge GPIO registers\n"
135              "   -r | --rcba:                      dump soutbridge RCBA registers\n"
136              "   -p | --pmbase:                    dump soutbridge Power Management registers\n\n"
137              "   -m | --mchbar:                    dump northbridge Memory Controller registers\n"
138              "   -e | --epbar:                     dump northbridge EPBAR registers\n"
139              "   -d | --dmibar:                    dump northbridge DMIBAR registers\n"
140              "   -P | --pciexpress:                dump northbridge PCIEXBAR registers\n\n"
141              "   -M | --msrs:                      dump CPU MSRs\n"
142              "   -a | --all:                       dump all known registers\n"
143              "\n");
144         exit(1);
145 }
146
147 int main(int argc, char *argv[])
148 {
149         struct pci_access *pacc;
150         struct pci_dev *sb = NULL, *nb, *dev;
151         int i, opt, option_index = 0;
152         unsigned int id;
153
154         char *sbname = "unknown", *nbname = "unknown";
155
156         int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
157         int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
158         int dump_pciexbar = 0, dump_coremsrs = 0;
159
160         static struct option long_options[] = {
161                 {"version", 0, 0, 'v'},
162                 {"help", 0, 0, 'h'},
163                 {"gpios", 0, 0, 'g'},
164                 {"mchbar", 0, 0, 'm'},
165                 {"rcba", 0, 0, 'r'},
166                 {"pmbase", 0, 0, 'p'},
167                 {"epbar", 0, 0, 'e'},
168                 {"dmibar", 0, 0, 'd'},
169                 {"pciexpress", 0, 0, 'P'},
170                 {"msrs", 0, 0, 'M'},
171                 {"all", 0, 0, 'a'},
172                 {0, 0, 0, 0}
173         };
174
175         while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
176                                   long_options, &option_index)) != EOF) {
177                 switch (opt) {
178                 case 'v':
179                         print_version();
180                         exit(0);
181                         break;
182                 case 'g':
183                         dump_gpios = 1;
184                         break;
185                 case 'm':
186                         dump_mchbar = 1;
187                         break;
188                 case 'r':
189                         dump_rcba = 1;
190                         break;
191                 case 'p':
192                         dump_pmbase = 1;
193                         break;
194                 case 'e':
195                         dump_epbar = 1;
196                         break;
197                 case 'd':
198                         dump_dmibar = 1;
199                         break;
200                 case 'P':
201                         dump_pciexbar = 1;
202                         break;
203                 case 'M':
204                         dump_coremsrs = 1;
205                         break;
206                 case 'a':
207                         dump_gpios = 1;
208                         dump_mchbar = 1;
209                         dump_rcba = 1;
210                         dump_pmbase = 1;
211                         dump_epbar = 1;
212                         dump_dmibar = 1;
213                         dump_pciexbar = 1;
214                         dump_coremsrs = 1;
215                         break;
216                 case 'h':
217                 case '?':
218                 default:
219                         print_usage(argv[0]);
220                         exit(0);
221                         break;
222                 }
223         }
224
225 #if defined(__FreeBSD__)
226         int io_fd;
227 #endif
228
229 #if defined(__FreeBSD__)
230         if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
231                 perror("/dev/io");
232 #else
233         if (iopl(3)) {
234                 perror("iopl");
235 #endif
236                 printf("You need to be root.\n");
237                 exit(1);
238         }
239
240 #ifndef __DARWIN__
241         if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
242                 perror("Can not open /dev/mem");
243                 exit(1);
244         }
245 #endif
246
247         pacc = pci_alloc();
248         pci_init(pacc);
249         pci_scan_bus(pacc);
250
251         /* Find the required devices */
252         for (dev = pacc->devices; dev; dev = dev->next) {
253                 pci_fill_info(dev, PCI_FILL_CLASS);
254                 /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
255                 if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
256                         if (sb == NULL)
257                                 sb = dev;
258                         else
259                                 fprintf(stderr, "Multiple devices with class ID"
260                                         " 0x0601, using %02x%02x:%02x.%02x\n",
261                                         dev->domain, dev->bus, dev->dev,
262                                         dev->func);
263                 }
264         }
265
266         if (!sb) {
267                 printf("No southbridge found.\n");
268                 exit(1);
269         }
270
271         pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
272
273         if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
274                 printf("Not an Intel(R) southbridge.\n");
275                 exit(1);
276         }
277
278         nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
279         if (!nb) {
280                 printf("No northbridge found.\n");
281                 exit(1);
282         }
283
284         pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
285
286         if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
287                 printf("Not an Intel(R) northbridge.\n");
288                 exit(1);
289         }
290
291         id = cpuid(1);
292
293         /* Intel has suggested applications to display the family of a CPU as
294          * the sum of the "Family" and the "Extended Family" fields shown
295          * above, and the model as the sum of the "Model" and the 4-bit
296          * left-shifted "Extended Model" fields.
297          * http://download.intel.com/design/processor/applnots/24161832.pdf
298          */
299         printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
300                         (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
301                         ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
302
303         /* Determine names */
304         for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
305                 if (nb->device_id == supported_chips_list[i].device_id)
306                         nbname = supported_chips_list[i].name;
307         for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
308                 if (sb->device_id == supported_chips_list[i].device_id)
309                         sbname = supported_chips_list[i].name;
310
311         printf("Intel Northbridge: %04x:%04x (%s)\n",
312                 nb->vendor_id, nb->device_id, nbname);
313
314         printf("Intel Southbridge: %04x:%04x (%s)\n",
315                 sb->vendor_id, sb->device_id, sbname);
316
317         /* Now do the deed */
318
319         if (dump_gpios) {
320                 print_gpios(sb);
321                 printf("\n\n");
322         }
323
324         if (dump_rcba) {
325                 print_rcba(sb);
326                 printf("\n\n");
327         }
328
329         if (dump_pmbase) {
330                 print_pmbase(sb, pacc);
331                 printf("\n\n");
332         }
333
334         if (dump_mchbar) {
335                 print_mchbar(nb, pacc);
336                 printf("\n\n");
337         }
338
339         if (dump_epbar) {
340                 print_epbar(nb);
341                 printf("\n\n");
342         }
343
344         if (dump_dmibar) {
345                 print_dmibar(nb);
346                 printf("\n\n");
347         }
348
349         if (dump_pciexbar) {
350                 print_pciexbar(nb);
351                 printf("\n\n");
352         }
353
354         if (dump_coremsrs) {
355                 print_intel_core_msrs();
356                 printf("\n\n");
357         }
358
359         /* Clean up */
360         pci_free_dev(nb);
361         // pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
362         pci_cleanup(pacc);
363
364         return 0;
365 }