util/inteltool/cpu.c

   1 /*
   2  * inteltool - dump all registers on an Intel CPU + chipset based system.
   3  *
   4  * Copyright (C) 2008-2010 by coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <fcntl.h>
  21 #include <unistd.h>
  22 #include <stdio.h>
  23 #include <stdlib.h>
  24 #include <string.h>
  25 #include <errno.h>
  26
  27 #include "inteltool.h"
  28
  29 int fd_msr;
  30
  31 unsigned int cpuid(unsigned int op)
  32 {
  33         uint32_t ret;
  34
  35 #if defined(__DARWIN__) && !defined(__LP64__)
  36         asm volatile (
  37                 "pushl %%ebx    \n"
  38                 "cpuid          \n"
  39                 "popl %%ebx     \n"
  40                 : "=a" (ret) : "a" (op) : "%ecx", "%edx"
  41         );
  42 #else
  43         asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx");
  44 #endif
  45
  46         return ret;
  47 }
  48
  49 #ifndef __DARWIN__
  50 int msr_readerror = 0;
  51
  52 msr_t rdmsr(int addr)
  53 {
  54         uint8_t buf[8];
  55         msr_t msr = { 0xffffffff, 0xffffffff };
  56
  57         if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
  58                 perror("Could not lseek() to MSR");
  59                 close(fd_msr);
  60                 exit(1);
  61         }
  62
  63         if (read(fd_msr, buf, 8) == 8) {
  64                 msr.lo = *(uint32_t *)buf;
  65                 msr.hi = *(uint32_t *)(buf + 4);
  66
  67                 return msr;
  68         }
  69
  70         if (errno == 5) {
  71                 printf(" (*)"); // Not all bits of the MSR could be read
  72                 msr_readerror = 1;
  73         } else {
  74                 // A severe error.
  75                 perror("Could not read() MSR");
  76                 close(fd_msr);
  77                 exit(1);
  78         }
  79
  80         return msr;
  81 }
  82 #endif
  83
  84 int print_intel_core_msrs(void)
  85 {
  86         unsigned int i, core, id;
  87         msr_t msr;
  88
  89 #define IA32_PLATFORM_ID                0x0017
  90 #define EBL_CR_POWERON                  0x002a
  91 #define FSB_CLK_STS                     0x00cd
  92 #define IA32_TIME_STAMP_COUNTER         0x0010
  93 #define IA32_APIC_BASE                  0x001b
  94
  95         typedef struct {
  96                 int number;
  97                 char *name;
  98         } msr_entry_t;
  99
 100         static const msr_entry_t model6bx_global_msrs[] = {
 101                 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
 102                 { 0x0017, "IA32_PLATFORM_ID" },
 103                 { 0x001b, "IA32_APIC_BASE" },
 104                 { 0x002a, "EBL_CR_POWERON" },
 105                 { 0x0033, "TEST_CTL" },
 106                 { 0x003f, "THERM_DIODE_OFFSET" },
 107                 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
 108                 { 0x008b, "IA32_BIOS_SIGN_ID" },
 109                 { 0x00c1, "PERFCTR0" },
 110                 { 0x00c2, "PERFCTR1" },
 111                 { 0x011e, "BBL_CR_CTL3" },
 112                 { 0x0179, "IA32_MCG_CAP" },
 113                 { 0x017a, "IA32_MCG_STATUS" },
 114                 { 0x0198, "IA32_PERF_STATUS" },
 115                 { 0x0199, "IA32_PERF_CONTROL" },
 116                 { 0x019a, "IA32_CLOCK_MODULATION" },
 117                 { 0x01a0, "IA32_MISC_ENABLES" },
 118                 { 0x01d9, "IA32_DEBUGCTL" },
 119                 { 0x0200, "IA32_MTRR_PHYSBASE0" },
 120                 { 0x0201, "IA32_MTRR_PHYSMASK0" },
 121                 { 0x0202, "IA32_MTRR_PHYSBASE1" },
 122                 { 0x0203, "IA32_MTRR_PHYSMASK1" },
 123                 { 0x0204, "IA32_MTRR_PHYSBASE2" },
 124                 { 0x0205, "IA32_MTRR_PHYSMASK2" },
 125                 { 0x0206, "IA32_MTRR_PHYSBASE3" },
 126                 { 0x0207, "IA32_MTRR_PHYSMASK3" },
 127                 { 0x0208, "IA32_MTRR_PHYSBASE4" },
 128                 { 0x0209, "IA32_MTRR_PHYSMASK4" },
 129                 { 0x020a, "IA32_MTRR_PHYSBASE5" },
 130                 { 0x020b, "IA32_MTRR_PHYSMASK5" },
 131                 { 0x020c, "IA32_MTRR_PHYSBASE6" },
 132                 { 0x020d, "IA32_MTRR_PHYSMASK6" },
 133                 { 0x020e, "IA32_MTRR_PHYSBASE7" },
 134                 { 0x020f, "IA32_MTRR_PHYSMASK7" },
 135                 { 0x0250, "IA32_MTRR_FIX64K_00000" },
 136                 { 0x0258, "IA32_MTRR_FIX16K_80000" },
 137                 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
 138                 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
 139                 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
 140                 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
 141                 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
 142                 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
 143                 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
 144                 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
 145                 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
 146                 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
 147                 { 0x0400, "IA32_MC0_CTL" },
 148                 { 0x0401, "IA32_MC0_STATUS" },
 149                 { 0x0402, "IA32_MC0_ADDR" },
 150                 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
 151                 { 0x040c, "IA32_MC4_CTL" },
 152                 { 0x040d, "IA32_MC4_STATUS" },
 153                 { 0x040e, "IA32_MC4_ADDR" },
 154                 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
 155         };
 156
 157         static const msr_entry_t model6ex_global_msrs[] = {
 158                 { 0x0017, "IA32_PLATFORM_ID" },
 159                 { 0x002a, "EBL_CR_POWERON" },
 160                 { 0x00cd, "FSB_CLOCK_STS" },
 161                 { 0x00ce, "FSB_CLOCK_VCC" },
 162                 { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" },
 163                 { 0x00e3, "PMG_IO_BASE_ADDR" },
 164                 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
 165                 { 0x00ee, "EXT_CONFIG" },
 166                 { 0x011e, "BBL_CR_CTL3" },
 167                 { 0x0194, "CLOCK_FLEX_MAX" },
 168                 { 0x0198, "IA32_PERF_STATUS" },
 169                 { 0x01a0, "IA32_MISC_ENABLES" },
 170                 { 0x01aa, "PIC_SENS_CFG" },
 171                 { 0x0400, "IA32_MC0_CTL" },
 172                 { 0x0401, "IA32_MC0_STATUS" },
 173                 { 0x0402, "IA32_MC0_ADDR" },
 174                 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
 175                 { 0x040c, "IA32_MC4_CTL" },
 176                 { 0x040d, "IA32_MC4_STATUS" },
 177                 { 0x040e, "IA32_MC4_ADDR" },
 178                 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
 179         };
 180
 181         static const msr_entry_t model6ex_per_core_msrs[] = {
 182                 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
 183                 { 0x001b, "IA32_APIC_BASE" },
 184                 { 0x003a, "IA32_FEATURE_CONTROL" },
 185                 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
 186                 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
 187                 { 0x008b, "IA32_BIOS_SIGN_ID" },
 188                 { 0x00e7, "IA32_MPERF" },
 189                 { 0x00e8, "IA32_APERF" },
 190                 { 0x00fe, "IA32_MTRRCAP" },
 191                 { 0x015f, "DTS_CAL_CTRL" },
 192                 { 0x0179, "IA32_MCG_CAP" },
 193                 { 0x017a, "IA32_MCG_STATUS" },
 194                 { 0x0199, "IA32_PERF_CONTROL" },
 195                 { 0x019a, "IA32_CLOCK_MODULATION" },
 196                 { 0x019b, "IA32_THERM_INTERRUPT" },
 197                 { 0x019c, "IA32_THERM_STATUS" },
 198                 { 0x019d, "GV_THERM" },
 199                 { 0x01d9, "IA32_DEBUGCTL" },
 200                 { 0x0200, "IA32_MTRR_PHYSBASE0" },
 201                 { 0x0201, "IA32_MTRR_PHYSMASK0" },
 202                 { 0x0202, "IA32_MTRR_PHYSBASE1" },
 203                 { 0x0203, "IA32_MTRR_PHYSMASK1" },
 204                 { 0x0204, "IA32_MTRR_PHYSBASE2" },
 205                 { 0x0205, "IA32_MTRR_PHYSMASK2" },
 206                 { 0x0206, "IA32_MTRR_PHYSBASE3" },
 207                 { 0x0207, "IA32_MTRR_PHYSMASK3" },
 208                 { 0x0208, "IA32_MTRR_PHYSBASE4" },
 209                 { 0x0209, "IA32_MTRR_PHYSMASK4" },
 210                 { 0x020a, "IA32_MTRR_PHYSBASE5" },
 211                 { 0x020b, "IA32_MTRR_PHYSMASK5" },
 212                 { 0x020c, "IA32_MTRR_PHYSBASE6" },
 213                 { 0x020d, "IA32_MTRR_PHYSMASK6" },
 214                 { 0x020e, "IA32_MTRR_PHYSBASE7" },
 215                 { 0x020f, "IA32_MTRR_PHYSMASK7" },
 216                 { 0x0250, "IA32_MTRR_FIX64K_00000" },
 217                 { 0x0258, "IA32_MTRR_FIX16K_80000" },
 218                 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
 219                 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
 220                 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
 221                 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
 222                 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
 223                 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
 224                 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
 225                 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
 226                 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
 227                 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
 228                 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
 229         };
 230
 231         static const msr_entry_t model6fx_global_msrs[] = {
 232                 { 0x0017, "IA32_PLATFORM_ID" },
 233                 { 0x002a, "EBL_CR_POWERON" },
 234                 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
 235                 { 0x00a8, "EMTTM_CR_TABLE0" },
 236                 { 0x00a9, "EMTTM_CR_TABLE1" },
 237                 { 0x00aa, "EMTTM_CR_TABLE2" },
 238                 { 0x00ab, "EMTTM_CR_TABLE3" },
 239                 { 0x00ac, "EMTTM_CR_TABLE4" },
 240                 { 0x00ad, "EMTTM_CR_TABLE5" },
 241                 { 0x00cd, "FSB_CLOCK_STS" },
 242                 { 0x00e2, "PMG_CST_CONFIG_CONTROL" },
 243                 { 0x00e3, "PMG_IO_BASE_ADDR" },
 244                 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
 245                 { 0x00ee, "EXT_CONFIG" },
 246                 { 0x011e, "BBL_CR_CTL3" },
 247                 { 0x0194, "CLOCK_FLEX_MAX" },
 248                 { 0x0198, "IA32_PERF_STATUS" },
 249                 { 0x01a0, "IA32_MISC_ENABLES" },
 250                 { 0x01aa, "PIC_SENS_CFG" },
 251                 { 0x0400, "IA32_MC0_CTL" },
 252                 { 0x0401, "IA32_MC0_STATUS" },
 253                 { 0x0402, "IA32_MC0_ADDR" },
 254                 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
 255                 { 0x040c, "IA32_MC4_CTL" },
 256                 { 0x040d, "IA32_MC4_STATUS" },
 257                 { 0x040e, "IA32_MC4_ADDR" },
 258                 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
 259         };
 260
 261         static const msr_entry_t model6fx_per_core_msrs[] = {
 262                 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
 263                 { 0x001b, "IA32_APIC_BASE" },
 264                 { 0x003a, "IA32_FEATURE_CONTROL" },
 265                 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
 266                 { 0x008b, "IA32_BIOS_SIGN_ID" },
 267                 { 0x00e1, "SMM_CST_MISC_INFO" },
 268                 { 0x00e7, "IA32_MPERF" },
 269                 { 0x00e8, "IA32_APERF" },
 270                 { 0x00fe, "IA32_MTRRCAP" },
 271                 { 0x0179, "IA32_MCG_CAP" },
 272                 { 0x017a, "IA32_MCG_STATUS" },
 273                 { 0x0199, "IA32_PERF_CONTROL" },
 274                 { 0x019a, "IA32_THERM_CTL" },
 275                 { 0x019b, "IA32_THERM_INTERRUPT" },
 276                 { 0x019c, "IA32_THERM_STATUS" },
 277                 { 0x019d, "MSR_THERM2_CTL" },
 278                 { 0x01d9, "IA32_DEBUGCTL" },
 279                 { 0x0200, "IA32_MTRR_PHYSBASE0" },
 280                 { 0x0201, "IA32_MTRR_PHYSMASK0" },
 281                 { 0x0202, "IA32_MTRR_PHYSBASE1" },
 282                 { 0x0203, "IA32_MTRR_PHYSMASK1" },
 283                 { 0x0204, "IA32_MTRR_PHYSBASE2" },
 284                 { 0x0205, "IA32_MTRR_PHYSMASK2" },
 285                 { 0x0206, "IA32_MTRR_PHYSBASE3" },
 286                 { 0x0207, "IA32_MTRR_PHYSMASK3" },
 287                 { 0x0208, "IA32_MTRR_PHYSBASE4" },
 288                 { 0x0209, "IA32_MTRR_PHYSMASK4" },
 289                 { 0x020a, "IA32_MTRR_PHYSBASE5" },
 290                 { 0x020b, "IA32_MTRR_PHYSMASK5" },
 291                 { 0x020c, "IA32_MTRR_PHYSBASE6" },
 292                 { 0x020d, "IA32_MTRR_PHYSMASK6" },
 293                 { 0x020e, "IA32_MTRR_PHYSBASE7" },
 294                 { 0x020f, "IA32_MTRR_PHYSMASK7" },
 295                 { 0x0250, "IA32_MTRR_FIX64K_00000" },
 296                 { 0x0258, "IA32_MTRR_FIX16K_80000" },
 297                 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
 298                 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
 299                 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
 300                 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
 301                 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
 302                 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
 303                 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
 304                 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
 305                 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
 306                 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
 307                 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
 308         };
 309
 310         /* Pentium 4 and XEON */
 311         /*
 312          * All MSRs per
 313          *
 314          * Intel® 64 and IA-32 Architectures
 315          * Software Developer.s Manual
 316          * Volume 3B:
 317          * System Programming Guide, Part 2
 318          *
 319          * Table B-5
 320          */
 321         static const msr_entry_t modelf4x_global_msrs[] = {
 322                 { 0x0000, "IA32_P5_MC_ADDR" },
 323                 { 0x0001, "IA32_P5_MC_TYPE" },
 324                 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
 325                 { 0x0017, "IA32_PLATFORM_ID" },
 326                 { 0x002a, "MSR_EBC_HARD_POWERON" },
 327                 { 0x002b, "MSR_EBC_SOFT_POWRON" },
 328                 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
 329 // WRITE ONLY   { 0x0079, "IA32_BIOS_UPDT_TRIG" },
 330                 { 0x019c, "IA32_THERM_STATUS" },
 331                 { 0x019d, "MSR_THERM2_CTL" },
 332                 { 0x01a0, "IA32_MISC_ENABLE" },
 333                 { 0x01a1, "MSR_PLATFORM_BRV" },
 334                 { 0x0200, "IA32_MTRR_PHYSBASE0" },
 335                 { 0x0201, "IA32_MTRR_PHYSMASK0" },
 336                 { 0x0202, "IA32_MTRR_PHYSBASE1" },
 337                 { 0x0203, "IA32_MTRR_PHYSMASK1" },
 338                 { 0x0204, "IA32_MTRR_PHYSBASE2" },
 339                 { 0x0205, "IA32_MTRR_PHYSMASK2" },
 340                 { 0x0206, "IA32_MTRR_PHYSBASE3" },
 341                 { 0x0207, "IA32_MTRR_PHYSMASK3" },
 342                 { 0x0208, "IA32_MTRR_PHYSBASE4" },
 343                 { 0x0209, "IA32_MTRR_PHYSMASK4" },
 344                 { 0x020a, "IA32_MTRR_PHYSBASE5" },
 345                 { 0x020b, "IA32_MTRR_PHYSMASK5" },
 346                 { 0x020c, "IA32_MTRR_PHYSBASE6" },
 347                 { 0x020d, "IA32_MTRR_PHYSMASK6" },
 348                 { 0x020e, "IA32_MTRR_PHYSBASE7" },
 349                 { 0x020f, "IA32_MTRR_PHYSMASK7" },
 350                 { 0x0250, "IA32_MTRR_FIX64K_00000" },
 351                 { 0x0258, "IA32_MTRR_FIX16K_80000" },
 352                 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
 353                 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
 354                 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
 355                 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
 356                 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
 357                 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
 358                 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
 359                 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
 360                 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
 361                 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
 362                 { 0x0300, "MSR_BPU_COUNTER0" },
 363                 { 0x0301, "MSR_BPU_COUNTER1" },
 364                 { 0x0302, "MSR_BPU_COUNTER2" },
 365                 { 0x0303, "MSR_BPU_COUNTER3" },
 366                 /* Skipped through 0x3ff  for now*/
 367
 368         /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
 369          * set in MCX_STATUS */
 370                 { 0x400, "IA32_MC0_CTL" },
 371                 { 0x401, "IA32_MC0_STATUS" },
 372                 { 0x402, "IA32_MC0_ADDR" },
 373                 { 0x403, "IA32_MC0_MISC" },
 374                 { 0x404, "IA32_MC1_CTL" },
 375                 { 0x405, "IA32_MC1_STATUS" },
 376                 { 0x406, "IA32_MC1_ADDR" },
 377                 { 0x407, "IA32_MC1_MISC" },
 378                 { 0x408, "IA32_MC2_CTL" },
 379                 { 0x409, "IA32_MC2_STATUS" },
 380                 { 0x40a, "IA32_MC2_ADDR" },
 381                 { 0x40b, "IA32_MC2_MISC" },
 382                 { 0x40c, "IA32_MC3_CTL" },
 383                 { 0x40d, "IA32_MC3_STATUS" },
 384                 { 0x40e, "IA32_MC3_ADDR" },
 385                 { 0x40f, "IA32_MC3_MISC" },
 386                 { 0x410, "IA32_MC4_CTL" },
 387                 { 0x411, "IA32_MC4_STATUS" },
 388                 { 0x412, "IA32_MC4_ADDR" },
 389                 { 0x413, "IA32_MC4_MISC" },
 390         };
 391
 392         static const msr_entry_t modelf4x_per_core_msrs[] = {
 393                 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
 394                 { 0x001b, "IA32_APIC_BASE" },
 395                 { 0x003a, "IA32_FEATURE_CONTROL" },
 396                 { 0x008b, "IA32_BIOS_SIGN_ID" },
 397                 { 0x009b, "IA32_SMM_MONITOR_CTL" },
 398                 { 0x00fe, "IA32_MTRRCAP" },
 399                 { 0x0174, "IA32_SYSENTER_CS" },
 400                 { 0x0175, "IA32_SYSENTER_ESP" },
 401                 { 0x0176, "IA32_SYSENTER_EIP" },
 402                 { 0x0179, "IA32_MCG_CAP" },
 403                 { 0x017a, "IA32_MCG_STATUS" },
 404                 { 0x0180, "MSR_MCG_RAX" },
 405                 { 0x0181, "MSR_MCG_RBX" },
 406                 { 0x0182, "MSR_MCG_RCX" },
 407                 { 0x0183, "MSR_MCG_RDX" },
 408                 { 0x0184, "MSR_MCG_RSI" },
 409                 { 0x0185, "MSR_MCG_RDI" },
 410                 { 0x0186, "MSR_MCG_RBP" },
 411                 { 0x0187, "MSR_MCG_RSP" },
 412                 { 0x0188, "MSR_MCG_RFLAGS" },
 413                 { 0x0189, "MSR_MCG_RIP" },
 414                 { 0x018a, "MSR_MCG_MISC" },
 415                 // 0x18b-f Reserved
 416                 { 0x0190, "MSR_MCG_R8" },
 417                 { 0x0191, "MSR_MCG_R9" },
 418                 { 0x0192, "MSR_MCG_R10" },
 419                 { 0x0193, "MSR_MCG_R11" },
 420                 { 0x0194, "MSR_MCG_R12" },
 421                 { 0x0195, "MSR_MCG_R13" },
 422                 { 0x0196, "MSR_MCG_R14" },
 423                 { 0x0197, "MSR_MCG_R15" },
 424                 { 0x0198, "IA32_PERF_STATUS" },
 425                 { 0x0199, "IA32_PERF_CTL" },
 426                 { 0x019a, "IA32_CLOCK_MODULATION" },
 427                 { 0x019b, "IA32_THERM_INTERRUPT" },
 428                 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
 429                 { 0x01d7, "MSR_LER_FROM_LIP" },
 430                 { 0x01d8, "MSR_LER_TO_LIP" },
 431                 { 0x01d9, "MSR_DEBUGCTLA" },
 432                 { 0x01da, "MSR_LASTBRANCH_TOS" },
 433                 { 0x0277, "IA32_PAT" },
 434                 /** Virtualization
 435                 { 0x480, "IA32_VMX_BASIC" },
 436                   through
 437                 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
 438                   Not implemented in my CPU
 439                 */
 440                 { 0x0600, "IA32_DS_AREA" },
 441                 /* 0x0680 - 0x06cf Branch Records Skipped */
 442
 443         };
 444
 445
 446
 447         typedef struct {
 448                 unsigned int model;
 449                 const msr_entry_t *global_msrs;
 450                 unsigned int num_global_msrs;
 451                 const msr_entry_t *per_core_msrs;
 452                 unsigned int num_per_core_msrs;
 453         } cpu_t;
 454
 455         cpu_t cpulist[] = {
 456                 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
 457                 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
 458                 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
 459                 { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
 460         };
 461
 462         cpu_t *cpu = NULL;
 463
 464         /* Get CPU family and model, not the stepping
 465          * (TODO: extended family/model)
 466          */
 467         id = cpuid(1) & 0xff0;
 468         for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
 469                 if(cpulist[i].model == id) {
 470                         cpu = &cpulist[i];
 471                         break;
 472                 }
 473         }
 474
 475         if (!cpu) {
 476                 printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
 477                 return -1;
 478         }
 479
 480 #ifndef __DARWIN__
 481         fd_msr = open("/dev/cpu/0/msr", O_RDWR);
 482         if (fd_msr < 0) {
 483                 perror("Error while opening /dev/cpu/0/msr");
 484                 printf("Did you run 'modprobe msr'?\n");
 485                 return -1;
 486         }
 487 #endif
 488
 489         printf("\n===================== SHARED MSRs (All Cores) =====================\n");
 490
 491         for (i = 0; i < cpu->num_global_msrs; i++) {
 492                 msr = rdmsr(cpu->global_msrs[i].number);
 493                 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
 494                        cpu->global_msrs[i].number, msr.hi, msr.lo,
 495                        cpu->global_msrs[i].name);
 496         }
 497
 498         close(fd_msr);
 499
 500         for (core = 0; core < 8; core++) {
 501 #ifndef __DARWIN__
 502                 char msrfilename[64];
 503                 memset(msrfilename, 0, 64);
 504                 sprintf(msrfilename, "/dev/cpu/%d/msr", core);
 505
 506                 fd_msr = open(msrfilename, O_RDWR);
 507
 508                 /* If the file is not there, we're probably through. No error,
 509                  * since we successfully opened /dev/cpu/0/msr before.
 510                  */
 511                 if (fd_msr < 0)
 512                         break;
 513 #endif
 514                 if (cpu->num_per_core_msrs)
 515                         printf("\n====================== UNIQUE MSRs  (core %d) ======================\n", core);
 516
 517                 for (i = 0; i < cpu->num_per_core_msrs; i++) {
 518                         msr = rdmsr(cpu->per_core_msrs[i].number);
 519                         printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
 520                                cpu->per_core_msrs[i].number, msr.hi, msr.lo,
 521                                cpu->per_core_msrs[i].name);
 522                 }
 523 #ifndef __DARWIN__
 524                 close(fd_msr);
 525 #endif
 526         }
 527
 528 #ifndef __DARWIN__
 529         if (msr_readerror)
 530                 printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
 531 #endif
 532         return 0;
 533 }
 534
 535