2 * This file is part of the flashrom project.
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Contains the generic SPI framework
32 void spi_prettyprint_status_register(struct flashchip *flash);
34 int spi_command(unsigned int writecnt, unsigned int readcnt,
35 const unsigned char *writearr, unsigned char *readarr)
38 case BUS_TYPE_IT87XX_SPI:
39 return it8716f_spi_command(writecnt, readcnt, writearr,
41 case BUS_TYPE_ICH7_SPI:
42 case BUS_TYPE_ICH9_SPI:
43 case BUS_TYPE_VIA_SPI:
44 return ich_spi_command(writecnt, readcnt, writearr, readarr);
45 case BUS_TYPE_SB600_SPI:
46 return sb600_spi_command(writecnt, readcnt, writearr, readarr);
47 case BUS_TYPE_WBSIO_SPI:
48 return wbsio_spi_command(writecnt, readcnt, writearr, readarr);
51 ("%s called, but no SPI chipset/strapping detected\n",
57 static int spi_rdid(unsigned char *readarr, int bytes)
59 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
61 if (spi_command(sizeof(cmd), bytes, cmd, readarr))
63 printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
68 static int spi_rems(unsigned char *readarr)
70 const unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
72 if (spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr))
74 printf_debug("REMS returned %02x %02x.\n", readarr[0], readarr[1]);
78 static int spi_res(unsigned char *readarr)
80 const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
82 if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr))
84 printf_debug("RES returned %02x.\n", readarr[0]);
88 int spi_write_enable()
90 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
92 /* Send WREN (Write Enable) */
93 return spi_command(sizeof(cmd), 0, cmd, NULL);
96 int spi_write_disable()
98 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
100 /* Send WRDI (Write Disable) */
101 return spi_command(sizeof(cmd), 0, cmd, NULL);
104 static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
106 unsigned char readarr[4];
110 if (spi_rdid(readarr, bytes))
113 if (!oddparity(readarr[0]))
114 printf_debug("RDID byte 0 parity violation.\n");
116 /* Check if this is a continuation vendor ID */
117 if (readarr[0] == 0x7f) {
118 if (!oddparity(readarr[1]))
119 printf_debug("RDID byte 1 parity violation.\n");
120 manuf_id = (readarr[0] << 8) | readarr[1];
121 model_id = readarr[2];
124 model_id |= readarr[3];
127 manuf_id = readarr[0];
128 model_id = (readarr[1] << 8) | readarr[2];
131 printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, manuf_id,
134 if (manuf_id == flash->manufacture_id && model_id == flash->model_id) {
135 /* Print the status register to tell the
136 * user about possible write protection.
138 spi_prettyprint_status_register(flash);
143 /* Test if this is a pure vendor match. */
144 if (manuf_id == flash->manufacture_id &&
145 GENERIC_DEVICE_ID == flash->model_id)
151 int probe_spi_rdid(struct flashchip *flash)
153 return probe_spi_rdid_generic(flash, 3);
156 /* support 4 bytes flash ID */
157 int probe_spi_rdid4(struct flashchip *flash)
159 /* only some SPI chipsets support 4 bytes commands */
161 case BUS_TYPE_ICH7_SPI:
162 case BUS_TYPE_ICH9_SPI:
163 case BUS_TYPE_VIA_SPI:
164 case BUS_TYPE_SB600_SPI:
165 case BUS_TYPE_WBSIO_SPI:
166 return probe_spi_rdid_generic(flash, 4);
168 printf_debug("4b ID not supported on this SPI controller\n");
174 int probe_spi_rems(struct flashchip *flash)
176 unsigned char readarr[JEDEC_REMS_INSIZE];
177 uint32_t manuf_id, model_id;
179 if (spi_rems(readarr))
182 manuf_id = readarr[0];
183 model_id = readarr[1];
185 printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id,
188 if (manuf_id == flash->manufacture_id && model_id == flash->model_id) {
189 /* Print the status register to tell the
190 * user about possible write protection.
192 spi_prettyprint_status_register(flash);
197 /* Test if this is a pure vendor match. */
198 if (manuf_id == flash->manufacture_id &&
199 GENERIC_DEVICE_ID == flash->model_id)
205 int probe_spi_res(struct flashchip *flash)
207 unsigned char readarr[3];
210 /* Check if RDID was successful and did not return 0xff 0xff 0xff.
211 * In that case, RES is pointless.
213 if (!spi_rdid(readarr, 3) && ((readarr[0] != 0xff) ||
214 (readarr[1] != 0xff) || (readarr[2] != 0xff)))
217 if (spi_res(readarr))
220 model_id = readarr[0];
221 printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id);
222 if (model_id != flash->model_id)
225 /* Print the status register to tell the
226 * user about possible write protection.
228 spi_prettyprint_status_register(flash);
232 uint8_t spi_read_status_register()
234 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
235 unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
237 /* Read Status Register */
238 if (flashbus == BUS_TYPE_SB600_SPI) {
239 /* SB600 uses a different way to read status register. */
240 return sb600_read_status_register();
242 spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
248 /* Prettyprint the status register. Common definitions.
250 void spi_prettyprint_status_register_common(uint8_t status)
252 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
253 "%sset\n", (status & (1 << 5)) ? "" : "not ");
254 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
255 "%sset\n", (status & (1 << 4)) ? "" : "not ");
256 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
257 "%sset\n", (status & (1 << 3)) ? "" : "not ");
258 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
259 "%sset\n", (status & (1 << 2)) ? "" : "not ");
260 printf_debug("Chip status register: Write Enable Latch (WEL) is "
261 "%sset\n", (status & (1 << 1)) ? "" : "not ");
262 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
263 "%sset\n", (status & (1 << 0)) ? "" : "not ");
266 /* Prettyprint the status register. Works for
270 void spi_prettyprint_status_register_st_m25p(uint8_t status)
272 printf_debug("Chip status register: Status Register Write Disable "
273 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
274 printf_debug("Chip status register: Bit 6 is "
275 "%sset\n", (status & (1 << 6)) ? "" : "not ");
276 spi_prettyprint_status_register_common(status);
279 /* Prettyprint the status register. Works for
282 void spi_prettyprint_status_register_sst25vf016(uint8_t status)
284 const char *bpt[] = {
293 printf_debug("Chip status register: Block Protect Write Disable "
294 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
295 printf_debug("Chip status register: Auto Address Increment Programming "
296 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
297 spi_prettyprint_status_register_common(status);
298 printf_debug("Resulting block protection : %s\n",
299 bpt[(status & 0x1c) >> 2]);
302 void spi_prettyprint_status_register(struct flashchip *flash)
306 status = spi_read_status_register();
307 printf_debug("Chip status register is %02x\n", status);
308 switch (flash->manufacture_id) {
310 if (((flash->model_id & 0xff00) == 0x2000) ||
311 ((flash->model_id & 0xff00) == 0x2500))
312 spi_prettyprint_status_register_st_m25p(status);
315 if ((flash->model_id & 0xff00) == 0x2000)
316 spi_prettyprint_status_register_st_m25p(status);
319 if (flash->model_id == SST_25VF016B)
320 spi_prettyprint_status_register_sst25vf016(status);
325 int spi_chip_erase_60(struct flashchip *flash)
327 const unsigned char cmd[JEDEC_CE_60_OUTSIZE] = {JEDEC_CE_60};
330 result = spi_disable_blockprotect();
332 printf_debug("spi_disable_blockprotect failed\n");
335 result = spi_write_enable();
337 printf_debug("spi_write_enable failed\n");
340 /* Send CE (Chip Erase) */
341 result = spi_command(sizeof(cmd), 0, cmd, NULL);
343 printf_debug("spi_chip_erase_60 failed sending erase\n");
346 /* Wait until the Write-In-Progress bit is cleared.
347 * This usually takes 1-85 s, so wait in 1 s steps.
349 /* FIXME: We assume spi_read_status_register will never fail. */
350 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
355 int spi_chip_erase_c7(struct flashchip *flash)
357 const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 };
360 result = spi_disable_blockprotect();
362 printf_debug("spi_disable_blockprotect failed\n");
365 result = spi_write_enable();
367 printf_debug("spi_write_enable failed\n");
370 /* Send CE (Chip Erase) */
371 result = spi_command(sizeof(cmd), 0, cmd, NULL);
373 printf_debug("spi_chip_erase_60 failed sending erase\n");
376 /* Wait until the Write-In-Progress bit is cleared.
377 * This usually takes 1-85 s, so wait in 1 s steps.
379 /* FIXME: We assume spi_read_status_register will never fail. */
380 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
385 int spi_chip_erase_60_c7(struct flashchip *flash)
388 result = spi_chip_erase_60(flash);
390 printf_debug("spi_chip_erase_60 failed, trying c7\n");
391 result = spi_chip_erase_c7(flash);
396 int spi_block_erase_52(const struct flashchip *flash, unsigned long addr)
398 unsigned char cmd[JEDEC_BE_52_OUTSIZE] = {JEDEC_BE_52};
400 cmd[1] = (addr & 0x00ff0000) >> 16;
401 cmd[2] = (addr & 0x0000ff00) >> 8;
402 cmd[3] = (addr & 0x000000ff);
404 /* Send BE (Block Erase) */
405 spi_command(sizeof(cmd), 0, cmd, NULL);
406 /* Wait until the Write-In-Progress bit is cleared.
407 * This usually takes 100-4000 ms, so wait in 100 ms steps.
409 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
414 /* Block size is usually
417 * 4-32k non-uniform for EON
419 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
421 unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 };
423 cmd[1] = (addr & 0x00ff0000) >> 16;
424 cmd[2] = (addr & 0x0000ff00) >> 8;
425 cmd[3] = (addr & 0x000000ff);
427 /* Send BE (Block Erase) */
428 spi_command(sizeof(cmd), 0, cmd, NULL);
429 /* Wait until the Write-In-Progress bit is cleared.
430 * This usually takes 100-4000 ms, so wait in 100 ms steps.
432 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
437 int spi_chip_erase_d8(struct flashchip *flash)
440 int total_size = flash->total_size * 1024;
441 int erase_size = 64 * 1024;
443 spi_disable_blockprotect();
445 printf("Erasing chip: \n");
447 for (i = 0; i < total_size / erase_size; i++) {
448 rc = spi_block_erase_d8(flash, i * erase_size);
450 printf("Error erasing block at 0x%x\n", i);
460 /* Sector size is usually 4k, though Macronix eliteflash has 64k */
461 int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
463 unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE };
464 cmd[1] = (addr & 0x00ff0000) >> 16;
465 cmd[2] = (addr & 0x0000ff00) >> 8;
466 cmd[3] = (addr & 0x000000ff);
469 /* Send SE (Sector Erase) */
470 spi_command(sizeof(cmd), 0, cmd, NULL);
471 /* Wait until the Write-In-Progress bit is cleared.
472 * This usually takes 15-800 ms, so wait in 10 ms steps.
474 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
479 int spi_write_status_enable()
481 const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
483 /* Send EWSR (Enable Write Status Register). */
484 return spi_command(JEDEC_EWSR_OUTSIZE, JEDEC_EWSR_INSIZE, cmd, NULL);
488 * This is according the SST25VF016 datasheet, who knows it is more
489 * generic that this...
491 int spi_write_status_register(int status)
493 const unsigned char cmd[JEDEC_WRSR_OUTSIZE] =
494 { JEDEC_WRSR, (unsigned char)status };
496 /* Send WRSR (Write Status Register) */
497 return spi_command(sizeof(cmd), 0, cmd, NULL);
500 void spi_byte_program(int address, uint8_t byte)
502 const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {
504 (address >> 16) & 0xff,
505 (address >> 8) & 0xff,
506 (address >> 0) & 0xff,
510 /* Send Byte-Program */
511 spi_command(sizeof(cmd), 0, cmd, NULL);
514 int spi_disable_blockprotect(void)
519 status = spi_read_status_register();
520 /* If there is block protection in effect, unprotect it first. */
521 if ((status & 0x3c) != 0) {
522 printf_debug("Some block protection in effect, disabling\n");
523 result = spi_write_status_enable();
525 printf_debug("spi_write_status_enable failed\n");
528 result = spi_write_status_register(status & ~0x3c);
530 printf_debug("spi_write_status_register failed\n");
537 int spi_nbyte_read(int address, uint8_t *bytes, int len)
539 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
541 (address >> 16) & 0xff,
542 (address >> 8) & 0xff,
543 (address >> 0) & 0xff,
547 return spi_command(sizeof(cmd), len, cmd, bytes);
550 int spi_chip_read(struct flashchip *flash, uint8_t *buf)
553 case BUS_TYPE_IT87XX_SPI:
554 return it8716f_spi_chip_read(flash, buf);
555 case BUS_TYPE_SB600_SPI:
556 return sb600_spi_read(flash, buf);
557 case BUS_TYPE_ICH7_SPI:
558 case BUS_TYPE_ICH9_SPI:
559 case BUS_TYPE_VIA_SPI:
560 return ich_spi_read(flash, buf);
561 case BUS_TYPE_WBSIO_SPI:
562 return wbsio_spi_read(flash, buf);
565 ("%s called, but no SPI chipset/strapping detected\n",
572 int spi_chip_write(struct flashchip *flash, uint8_t *buf)
575 case BUS_TYPE_IT87XX_SPI:
576 return it8716f_spi_chip_write(flash, buf);
577 case BUS_TYPE_SB600_SPI:
578 return sb600_spi_write(flash, buf);
579 case BUS_TYPE_ICH7_SPI:
580 case BUS_TYPE_ICH9_SPI:
581 case BUS_TYPE_VIA_SPI:
582 return ich_spi_write(flash, buf);
583 case BUS_TYPE_WBSIO_SPI:
584 return wbsio_spi_write(flash, buf);
587 ("%s called, but no SPI chipset/strapping detected\n",