2 *****************************************************************************
4 * Copyright (c) 2011, Advanced Micro Devices, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
15 * its contributors may be used to endorse or promote products derived
16 * from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * ***************************************************************************
33 #define BIOS_SIZE 0x04 //04 - 1MB
34 #define LEGACY_FREE 0x00
35 //#define ACPI_SLEEP_TRAP 0x01
36 //#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
39 * Module Specific Defines for platform BIOS
44 * PCIEX_BASE_ADDRESS - Define PCIE base address
46 * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
48 #ifdef MOVE_PCIEBAR_TO_F0000000
49 #define PCIEX_BASE_ADDRESS 0xF7000000
51 #define PCIEX_BASE_ADDRESS 0xF8000000
55 * SMBUS0_BASE_ADDRESS - Smbus base address
58 #ifndef SMBUS0_BASE_ADDRESS
59 #define SMBUS0_BASE_ADDRESS 0xB00
63 * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
66 #ifndef SMBUS1_BASE_ADDRESS
67 #define SMBUS1_BASE_ADDRESS 0xB20
71 * GEC_BASE_ADDRESS - Gec Shadow ROM base address
74 #ifndef GEC_BASE_ADDRESS
75 #define GEC_BASE_ADDRESS 0xFED61000
80 * SIO_PME_BASE_ADDRESS - Super IO PME base address
83 #ifndef SIO_PME_BASE_ADDRESS
84 #define SIO_PME_BASE_ADDRESS 0xE00
88 * SPI_BASE_ADDRESS - SPI controller (ROM) base address
91 #ifndef SPI_BASE_ADDRESS
92 #define SPI_BASE_ADDRESS 0xFEC10000
96 * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
99 #ifndef WATCHDOG_TIMER_BASE_ADDRESS
100 #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
104 * HPET_BASE_ADDRESS - HPET base address
107 #ifndef HPET_BASE_ADDRESS
108 #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
112 * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
116 #define ACPI_BLK_BASE 0x400
118 #define ACPI_BLK_BASE 0x800
121 #define PM1_STATUS_OFFSET 0x00
122 #define PM1_ENABLE_OFFSET 0x02
123 #define PM1_CONTROL_OFFSET 0x04
124 #define PM_TIMER_OFFSET 0x08
125 #define CPU_CONTROL_OFFSET 0x10
126 #define EVENT_STATUS_OFFSET 0x20
127 #define EVENT_ENABLE_OFFSET 0x24
130 * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
133 #define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
136 * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
139 #define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
142 * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
145 #define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
148 * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
151 #define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
154 * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
157 #define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
160 * SMI_CMD_PORT - ACPI SMI Command block base address
163 #define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
166 * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
169 #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
172 * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
173 * Define value for SSID while SATA controller set to IDE mode.
175 #ifndef SATA_IDE_MODE_SSID
176 #define SATA_IDE_MODE_SSID 0x43901002
180 * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
181 * Define value for SSID while SATA controller set to RAID mode.
183 #ifndef SATA_RAID_MODE_SSID
184 #define SATA_RAID_MODE_SSID 0x43921002
188 * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
189 * Define value for SSID while SATA controller set to RAID5 mode.
191 #ifndef SATA_RAID5_MODE_SSID
192 #define SATA_RAID5_MODE_SSID 0x43931002
196 * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
197 * Define value for SSID while SATA controller set to AHCI mode.
199 #ifndef SATA_AHCI_SSID
200 #define SATA_AHCI_SSID 0x43911002
204 * OHCI_SSID - All SB OHCI controllers SSID value.
208 #define OHCI_SSID 0x43971002
212 * EHCI_SSID - All SB EHCI controllers SSID value.
216 #define EHCI_SSID 0x43961002
220 * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
224 #define OHCI4_SSID 0x43991002
228 * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
232 #define SMBUS_SSID 0x43851002
236 * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
240 #define IDE_SSID 0x439C1002
244 * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
248 #define AZALIA_SSID 0x43831002
252 * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
256 #define LPC_SSID 0x439D1002
260 * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
264 #define PCIB_SSID 0x43841002
268 * USB_PLL_Voltage - CG2 Clock voltage setting.
271 #ifndef USB_PLL_Voltage
272 #define USB_PLL_Voltage 0x10
276 * Spread_Spectrum_Type
278 * - 0 : Normal platform
279 * - 1 : Ontario platform
281 #ifndef Spread_Spectrum_Type
282 #define Spread_Spectrum_Type 0x00