7 * Technology Software DRAM Init for DDR3 Recovery
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Proc/Recovery/Mem)
12 * @e \$Revision: 49896 $ @e \$Date: 2011-03-30 02:18:18 -0600 (Wed, 30 Mar 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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21 * modification, are permitted provided that the following conditions are met:
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40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
48 *----------------------------------------------------------------------------
51 *----------------------------------------------------------------------------
57 #include "OptionMemory.h"
68 #define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE
69 /*----------------------------------------------------------------------------
70 * DEFINITIONS AND MACROS
72 *----------------------------------------------------------------------------
75 /*----------------------------------------------------------------------------
76 * TYPEDEFS AND STRUCTURES
78 *----------------------------------------------------------------------------
81 /*----------------------------------------------------------------------------
82 * PROTOTYPES OF LOCAL FUNCTIONS
84 *----------------------------------------------------------------------------
88 /*----------------------------------------------------------------------------
91 *----------------------------------------------------------------------------
96 /* -----------------------------------------------------------------------------*/
99 * This function initiates software DRAM init
101 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
107 IN OUT MEM_TECH_BLOCK *TechPtr
111 MEM_DATA_STRUCT *MemPtr;
114 NBPtr = TechPtr->NBPtr;
115 MemPtr = NBPtr->MemPtr;
117 IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n");
118 IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for DCT%d\n", NBPtr->Dct);
119 // 3.Program F2x[1,0]7C[EnDramInit]=1
120 NBPtr->SetBitField (NBPtr, BFEnDramInit, 1);
123 MemRecUWait10ns (20000, MemPtr);
125 NBPtr->SetBitField (NBPtr, BFDeassertMemRstX, 1);
128 MemRecUWait10ns (50000, MemPtr);
130 // 7.NOP or deselect & take CKE high
131 NBPtr->SetBitField (NBPtr, BFAssertCke, 1);
134 MemRecUWait10ns (36, MemPtr);
136 // The following steps are performed with registered DIMMs only and
137 // must be done for each chip select pair:
139 if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
140 MemRecTDramControlRegInit3 (TechPtr);
143 for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
144 if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) {
146 // Set Dram ODT per ChipSel
147 NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, ChipSel, (NBPtr->DimmToBeUsed << 1));
149 NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
151 MemRecTEMRS23 (TechPtr);
152 NBPtr->SendMrsCmd (NBPtr);
154 // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
155 MemRecTEMRS33 (TechPtr);
156 NBPtr->SendMrsCmd (NBPtr);
159 MemRecTEMRS13 (TechPtr);
160 NBPtr->SendMrsCmd (NBPtr);
162 // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
163 MemRecTMRS3 (TechPtr);
164 NBPtr->SendMrsCmd (NBPtr);
167 MemRecUWait10ns (50000, MemPtr);
169 if (NBPtr->ChannelPtr->RegDimmPresent == 0) {
175 // 17.Send two ZQCL commands (to even then odd chip select)
176 NBPtr->sendZQCmd (NBPtr);
177 NBPtr->sendZQCmd (NBPtr);
179 // 18.Program F2x[1,0]7C[EnDramInit]=0
180 NBPtr->SetBitField (NBPtr, BFEnDramInit, 0);
181 IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
184 /* -----------------------------------------------------------------------------*/
187 * This function calculates the EMRS1 value
189 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
195 IN OUT MEM_TECH_BLOCK *TechPtr
203 NBPtr = TechPtr->NBPtr;
206 NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
210 // program MrsAddress[5,1]=output driver impedance control (DIC):
211 // based on F2x[1,0]84[DrvImpCtrl], which is 2'b01
212 MrsAddress |= ((UINT16) 1 << 1);
214 // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
215 // based on F2x[1,0]84[DramTerm], which is 3'b001 (60 Ohms)
216 if (!(NBPtr->IsSupported[CheckDramTerm])) {
217 DramTerm = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTerm);
219 DramTerm = NBPtr->PsPtr->DramTerm;
221 if ((DramTerm & 1) != 0) {
222 MrsAddress |= ((UINT16) 1 << 2);
224 if ((DramTerm & 2) != 0) {
225 MrsAddress |= ((UINT16) 1 << 6);
227 if ((DramTerm & 4) != 0) {
228 MrsAddress |= ((UINT16) 1 << 9);
231 // program MrsAddress[12]=output disable (QOFF):
232 // based on F2x[1,0]84[Qoff], which is 1'b0
234 // program MrsAddress[11]=TDQS:
235 // based on F2x[1,0]94[RDqsEn], which is 1'b0
237 NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
240 /* -----------------------------------------------------------------------------*/
243 * This function calculates the EMRS2 value
245 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
251 IN OUT MEM_TECH_BLOCK *TechPtr
258 NBPtr = TechPtr->NBPtr;
261 NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
263 // program MrsAddress[5:3]=CAS write latency (CWL):
264 // based on F2x[1,0]84[Tcwl], which is 3'b000
268 // program MrsAddress[6]=auto self refresh method (ASR):
269 // based on F2x[1,0]84[ASR], which is 1'b1
270 // program MrsAddress[7]=self refresh temperature range (SRT):
271 // based on F2x[1,0]84[SRT], which is also 1'b0
273 MrsAddress |= (UINT16) 1 << 6;
275 // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
276 // based on F2x[1,0]84[DramTermDyn]
278 if (!(NBPtr->IsSupported[CheckDramTermDyn])) {
279 DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn);
281 DramTermDyn = NBPtr->PsPtr->DynamicDramTerm;
283 MrsAddress |= (UINT16) DramTermDyn << 9;
284 NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
287 /* -----------------------------------------------------------------------------*/
290 * This function calculates the EMRS3 value
292 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
298 IN OUT MEM_TECH_BLOCK *TechPtr
303 NBPtr = TechPtr->NBPtr;
306 NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
308 // program MrsAddress[1:0]=multi purpose register address location
309 // (MPR Location):based on F2x[1,0]84[MprLoc], which is 0
310 // program MrsAddress[2]=multi purpose register
311 // (MPR):based on F2x[1,0]84[MprEn], which is also 0
313 NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
316 /* -----------------------------------------------------------------------------*/
319 * This sets MSS value
321 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
327 IN OUT MEM_TECH_BLOCK *TechPtr
333 NBPtr = TechPtr->NBPtr;
336 NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
338 // program MrsAddress[1:0]=burst length and control method
339 // (BL):based on F2x[1,0]84[BurstCtrl], which is 1'b0
343 // program MrsAddress[3]=1 (BT):interleaved
344 MrsAddress |= (UINT16) 1 << 3;
346 // program MrsAddress[6:4,2]=read CAS latency
347 // (CL):based on F2x[1,0]88[Tcl], which is 4'b0010
348 MrsAddress |= (UINT16) 2 << 4;
350 // program MrsAddress[11:9]=write recovery for auto-precharge
351 // (WR):based on F2x[1,0]84[Twr], which is 3'b010
353 MrsAddress |= (UINT16) 2 << 9;
355 // program MrsAddress[12]=0 (PPD):slow exit
357 // program MrsAddress[8]=1 (DLL):DLL reset
358 MrsAddress |= (UINT16) 1 << 8; // just issue DLL reset at first time
360 NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);