7 * S3 resume memory related functions.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Feat/S3)
12 * @e \$Revision: 51373 $ @e \$Date: 2011-04-21 13:10:59 -0600 (Thu, 21 Apr 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
49 /*----------------------------------------------------------------------------
50 * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
52 *----------------------------------------------------------------------------
55 /*-----------------------------------------------------------------------------
56 * DEFINITIONS AND MACROS
58 *-----------------------------------------------------------------------------
66 #define DCT0_NBPSTATE_SUPPORT_MASK 0x4
67 #define DCT1_NBPSTATE_SUPPORT_MASK 0x8
68 #define DCT0_DDR3_MASK 0x10
69 #define DCT1_DDR3_MASK 0x20
70 #define NODE_WITHOUT_DIMM_MASK 0x80
71 #define DCT0_ANY_DIMM_MASK 0x55
72 #define DCT1_ANY_DIMM_MASK 0xAA
73 #define ANY_DIMM_MASK 0xFF
75 #define DCT_PHY_FLAG 0
76 #define DCT_EXTRA_FLAG 1
77 #define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset)
79 /*----------------------------------------------------------------------------
80 * TYPEDEFS, STRUCTURES, ENUMS
82 *----------------------------------------------------------------------------
84 /// struct for all the descriptor for pre exit self refresh and post exit self refresh
85 typedef struct _DESCRIPTOR_GROUP {
86 PCI_DEVICE_DESCRIPTOR PCIDevice[2]; ///< PCI device descriptor
87 CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2]; ///< Conditional PCI device descriptor
88 MSR_DEVICE_DESCRIPTOR MSRDevice[2]; ///< MSR device descriptor
89 CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2]; ///< Conditional MSR device descriptor
92 /// Northbridge block to be used in S3 resume and save.
93 typedef struct _S3_MEM_NB_BLOCK {
94 UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap.
95 struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to the north bridge block.
96 VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register
97 VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting
98 VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting
99 UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register
100 BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh
101 VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base
102 AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device
105 /// Header for heap space to store the special case register.
106 typedef struct _S3_SPECIAL_CASE_HEAP_HEADER {
107 UINT8 Node; ///< Node ID for the the header
108 UINT8 Offset; ///< Offset for the target node
109 } S3_SPECIAL_CASE_HEAP_HEADER;
110 /*----------------------------------------------------------------------------
111 * FUNCTIONS PROTOTYPE
113 *----------------------------------------------------------------------------
117 IN AMD_CONFIG_PARAMS *StdHeader
122 IN AMD_CONFIG_PARAMS *StdHeader
127 IN AMD_CONFIG_PARAMS *StdHeader
131 MemFS3GetPciDeviceRegisterList (
132 IN PCI_DEVICE_DESCRIPTOR *Device,
133 OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
134 IN AMD_CONFIG_PARAMS *StdHeader
138 MemFS3GetCPciDeviceRegisterList (
139 IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
140 OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr,
141 IN AMD_CONFIG_PARAMS *StdHeader
145 MemFS3GetMsrDeviceRegisterList (
146 IN MSR_DEVICE_DESCRIPTOR *Device,
147 OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
148 IN AMD_CONFIG_PARAMS *StdHeader
152 MemFS3GetCMsrDeviceRegisterList (
153 IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
154 OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr,
155 IN AMD_CONFIG_PARAMS *StdHeader
159 MemFS3GetDeviceList (
160 IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
161 IN AMD_CONFIG_PARAMS *StdHeader
167 IN OUT MEM_DATA_STRUCT *MemPtr
172 IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
177 MemNS3ResumeClientNb (
178 IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
184 IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
189 MemNS3GetConPCIMaskNb (
190 IN OUT MEM_NB_BLOCK *NBPtr,
191 IN OUT DESCRIPTOR_GROUP *DescriptPtr
195 MemNS3GetConPCIMaskUnb (
196 IN OUT MEM_NB_BLOCK *NBPtr,
197 IN OUT DESCRIPTOR_GROUP *DescriptPtr
202 IN ACCESS_WIDTH AccessWidth,
205 IN OUT VOID *ConfigPtr
210 IN ACCESS_WIDTH AccessWidth,
213 IN OUT VOID *ConfigPtr
217 MemNS3GetBitFieldNb (
218 IN ACCESS_WIDTH AccessWidth,
221 IN OUT VOID *ConfigPtr
225 MemNS3SetBitFieldNb (
226 IN ACCESS_WIDTH AccessWidth,
229 IN OUT VOID *ConfigPtr
233 MemNS3RestoreScrubNb (
234 IN OUT MEM_NB_BLOCK *NBPtr,
240 IN OUT S3_MEM_NB_BLOCK **S3NBPtr,
241 IN OUT MEM_DATA_STRUCT **MemPtr,
242 IN OUT MEM_MAIN_DATA_BLOCK *mmData,
243 IN AMD_CONFIG_PARAMS *StdHeader
248 IN ACCESS_WIDTH AccessWidth,
251 IN OUT VOID *ConfigPtr
256 IN ACCESS_WIDTH AccessWidth,
259 IN OUT VOID *ConfigPtr
263 MemNS3SetDynModeChangeNb (
264 IN ACCESS_WIDTH AccessWidth,
267 IN OUT VOID *ConfigPtr
271 MemNS3DisableChannelNb (
272 IN ACCESS_WIDTH AccessWidth,
275 IN OUT VOID *ConfigPtr
279 MemNS3SetDisAutoCompUnb (
280 IN ACCESS_WIDTH AccessWidth,
283 IN OUT VOID *ConfigPtr
287 MemNS3SetPreDriverCalUnb (
288 IN ACCESS_WIDTH AccessWidth,
291 IN OUT VOID *ConfigPtr
295 MemNS3DctCfgSelectUnb (
296 IN OUT MEM_NB_BLOCK *NBPtr,
301 MemNS3GetNBPStateDepRegUnb (
302 IN ACCESS_WIDTH AccessWidth,
305 IN OUT VOID *ConfigPtr
309 MemNS3SetNBPStateDepRegUnb (
310 IN ACCESS_WIDTH AccessWidth,
313 IN OUT VOID *ConfigPtr
317 MemNS3SaveNBRegiserUnb (
318 IN ACCESS_WIDTH AccessWidth,
321 IN OUT VOID *ConfigPtr
325 MemNS3RestoreNBRegiserUnb (
326 IN ACCESS_WIDTH AccessWidth,
329 IN OUT VOID *ConfigPtr
333 MemNS3SetMemClkFreqValUnb (
334 IN ACCESS_WIDTH AccessWidth,
337 IN OUT VOID *ConfigPtr
341 MemNS3ChangeMemPStateContextNb (
342 IN ACCESS_WIDTH AccessWidth,
345 IN OUT VOID *ConfigPtr
349 MemNS3SetPhyClkDllFineClientNb (
350 IN ACCESS_WIDTH AccessWidth,
353 IN OUT VOID *ConfigPtr