7 * Technology Non-SPD Timings for DDR3
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Tech/DDR3)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
65 #define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE
66 /*----------------------------------------------------------------------------
67 * DEFINITIONS AND MACROS
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * TYPEDEFS AND STRUCTURES
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * PROTOTYPES OF LOCAL FUNCTIONS
81 *----------------------------------------------------------------------------
84 /*----------------------------------------------------------------------------
87 *----------------------------------------------------------------------------
90 /* -----------------------------------------------------------------------------*/
93 * This function adjusts the Twrwr value for DDR3.
95 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
101 IN OUT MEM_TECH_BLOCK *TechPtr
106 DCTPtr = TechPtr->NBPtr->DCTPtr;
108 // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved.
109 if (DCTPtr->Timings.Twrwr < 2) {
110 DCTPtr->Timings.Twrwr = 2;
111 } else if (DCTPtr->Timings.Twrwr > 10) {
112 DCTPtr->Timings.Twrwr = 10;
116 /* -----------------------------------------------------------------------------*/
119 * This function adjusts the Twrrd value for DDR3.
121 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
127 IN OUT MEM_TECH_BLOCK *TechPtr
132 DCTPtr = TechPtr->NBPtr->DCTPtr;
134 // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved.
135 if (DCTPtr->Timings.Twrrd < 2) {
136 DCTPtr->Timings.Twrrd = 2;
137 } else if (DCTPtr->Timings.Twrrd > 10) {
138 DCTPtr->Timings.Twrrd = 10;
142 /* -----------------------------------------------------------------------------*/
145 * This function gets the LD value for DDR3.
147 * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
149 * @return Value of LD
154 IN OUT MEM_TECH_BLOCK *TechPtr
159 NBPtr = TechPtr->NBPtr;
161 // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
162 // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
165 LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5);