7 * Platform specific settings for HY DDR3 U-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
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21 * modification, are permitted provided that the following conditions are met:
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23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
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31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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42 * ***************************************************************************
46 /* This file contains routine that add platform specific support L1 */
50 #include "AdvancedApi.h"
51 #include "PlatformMemoryConfiguration.h"
55 #include "cpuFamRegisters.h"
59 #include "GeneralServices.h"
64 #define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE
65 /*----------------------------------------------------------------------------
66 * DEFINITIONS AND MACROS
68 *----------------------------------------------------------------------------
71 /*----------------------------------------------------------------------------
72 * TYPEDEFS AND STRUCTURES
74 *----------------------------------------------------------------------------
77 /*----------------------------------------------------------------------------
78 * PROTOTYPES OF LOCAL FUNCTIONS
80 *----------------------------------------------------------------------------
85 IN OUT MEM_NB_BLOCK *NBPtr
90 MemPGetPORFreqLimitUHy3 (
91 IN OUT MEM_NB_BLOCK *NBPtr
94 *-----------------------------------------------------------------------------
97 *-----------------------------------------------------------------------------
99 STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
100 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
101 {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
102 {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
103 {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
106 /* -----------------------------------------------------------------------------*/
109 * This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
111 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
112 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
113 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
115 * @return AGESA_SUCCESS
120 MemPConstructPsUHy3 (
121 IN OUT MEM_DATA_STRUCT *MemPtr,
122 IN OUT CH_DEF_STRUCT *ChannelPtr,
123 IN OUT MEM_PS_BLOCK *PsPtr
126 ASSERT (MemPtr != 0);
127 ASSERT (ChannelPtr != 0);
129 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
130 return AGESA_UNSUPPORTED;
132 if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
133 return AGESA_UNSUPPORTED;
135 if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
136 return AGESA_UNSUPPORTED;
138 PsPtr->MemPDoPs = MemPDoPsUhy3;
139 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3;
140 return AGESA_SUCCESS;
143 /* -----------------------------------------------------------------------------*/
146 * This is function sets the platform specific settings for U-DDR3 HY DDR3
148 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
150 * @return TRUE - Find settings for corresponding platform and dimm population.
151 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
158 IN OUT MEM_NB_BLOCK *NBPtr
161 if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) {
168 /* -----------------------------------------------------------------------------*/
171 * This is function gets the POR speed limit for U-DDR3 HY
173 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
179 MemPGetPORFreqLimitUHy3 (
180 IN OUT MEM_NB_BLOCK *NBPtr
185 // Highest POR supported speed for Unbuffered dimm is 1333
187 MaxSpeed = DDR1333_FREQUENCY;
188 if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
189 NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
190 } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
191 // Unbuffered DDR3 at 333MHz is not supported
192 NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
193 PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
194 SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
195 // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
196 NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;