7 * Platform specific settings for HY DDR3 SO-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
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21 * modification, are permitted provided that the following conditions are met:
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23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
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31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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42 * ***************************************************************************
46 /* This file contains routine that add platform specific support L1 */
50 #include "AdvancedApi.h"
54 #include "cpuFamRegisters.h"
59 #include "OptionMemory.h"
60 #include "PlatformMemoryConfiguration.h"
65 #define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE
66 /*----------------------------------------------------------------------------
67 * DEFINITIONS AND MACROS
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * TYPEDEFS AND STRUCTURES
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * PROTOTYPES OF LOCAL FUNCTIONS
81 *----------------------------------------------------------------------------
86 IN OUT MEM_NB_BLOCK *NBPtr
91 MemPGetPORFreqLimitSHy3 (
92 IN OUT MEM_NB_BLOCK *NBPtr
95 *-----------------------------------------------------------------------------
98 *-----------------------------------------------------------------------------
100 STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = {
101 {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
102 {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
105 STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
106 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
107 {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
108 {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
109 {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
111 /* -----------------------------------------------------------------------------*/
114 * This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
116 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
117 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
118 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
120 * @return AGESA_SUCCESS
125 MemPConstructPsSHy3 (
126 IN OUT MEM_DATA_STRUCT *MemPtr,
127 IN OUT CH_DEF_STRUCT *ChannelPtr,
128 IN OUT MEM_PS_BLOCK *PsPtr
131 ASSERT (MemPtr != 0);
132 ASSERT (ChannelPtr != 0);
134 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
135 return AGESA_UNSUPPORTED;
137 if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
138 return AGESA_UNSUPPORTED;
140 if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
141 return AGESA_UNSUPPORTED;
143 PsPtr->MemPDoPs = MemPDoPsSHy3;
144 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3;
145 return AGESA_SUCCESS;
148 /* -----------------------------------------------------------------------------*/
151 * This is function sets the platform specific settings for S-DDR3 HY DDR3
153 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
155 * @return TRUE - Find settings for corresponding platform and dimm population.
156 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
163 IN OUT MEM_NB_BLOCK *NBPtr
166 CONST DRAM_TERM_ENTRY *DramTermPtr;
167 UINT8 MaxDimmsPerChannel;
168 UINT8 *DimmsPerChPtr;
173 DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL);
174 if (DimmsPerChPtr != NULL) {
175 MaxDimmsPerChannel = *DimmsPerChPtr;
177 MaxDimmsPerChannel = 2;
180 if (MaxDimmsPerChannel == 1) {
181 DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D);
182 DramTermPtr = HySDdr3DramTerm1D;
183 } else if (MaxDimmsPerChannel == 2) {
184 DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D);
185 DramTermPtr = HySDdr3DramTerm2D;
190 if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
197 /* -----------------------------------------------------------------------------*/
200 * This is function gets the POR speed limit for SO-DDR3 HY
202 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
208 MemPGetPORFreqLimitSHy3 (
209 IN OUT MEM_NB_BLOCK *NBPtr
214 // Highest POR supported speed for SODimm is 1333
216 MaxSpeed = DDR1333_FREQUENCY;
217 if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
218 NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;