7 * Platform specific settings for DR DDR2 U-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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42 * ***************************************************************************
46 /* This file contains routine that add platform specific support L1 */
50 #include "AdvancedApi.h"
52 #include "PlatformMemoryConfiguration.h"
55 #include "cpuFamRegisters.h"
63 #define FILECODE PROC_MEM_PS_DR_MPUDR2_FILECODE
64 /*----------------------------------------------------------------------------
65 * DEFINITIONS AND MACROS
67 *----------------------------------------------------------------------------
70 /*----------------------------------------------------------------------------
71 * TYPEDEFS AND STRUCTURES
73 *----------------------------------------------------------------------------
76 /*----------------------------------------------------------------------------
77 * PROTOTYPES OF LOCAL FUNCTIONS
79 *----------------------------------------------------------------------------
84 IN OUT MEM_NB_BLOCK *NBPtr
88 *-----------------------------------------------------------------------------
91 *-----------------------------------------------------------------------------
93 STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
94 {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
95 {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
96 {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
97 {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
98 {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
99 {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
100 {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
103 /* -----------------------------------------------------------------------------*/
106 * This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
108 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
109 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
110 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
112 * @return AGESA_SUCCESS
117 MemPConstructPsUDr2 (
118 IN OUT MEM_DATA_STRUCT *MemPtr,
119 IN OUT CH_DEF_STRUCT *ChannelPtr,
120 IN OUT MEM_PS_BLOCK *PsPtr
123 ASSERT (MemPtr != 0);
124 ASSERT (ChannelPtr != 0);
127 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
128 return AGESA_UNSUPPORTED;
130 if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
131 return AGESA_UNSUPPORTED;
133 if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
134 return AGESA_UNSUPPORTED;
136 PsPtr->MemPDoPs = MemPDoPsUDr2;
137 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
138 return AGESA_SUCCESS;
141 /* -----------------------------------------------------------------------------*/
144 * This is function sets the platform specific settings for U-DDR2 DR DDR2
146 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
148 * @return TRUE - Find settings for corresponding platform and dimm population.
149 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
156 IN OUT MEM_NB_BLOCK *NBPtr
159 if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {