7 * Platform specific settings for DR DDR3 R-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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42 * ***************************************************************************
46 /* This file contains routine that add platform specific support L1 */
50 #include "AdvancedApi.h"
54 #include "cpuFamRegisters.h"
59 #include "OptionMemory.h"
60 #include "PlatformMemoryConfiguration.h"
65 #define FILECODE PROC_MEM_PS_DR_MPRDR3_FILECODE
66 /*----------------------------------------------------------------------------
67 * DEFINITIONS AND MACROS
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * TYPEDEFS AND STRUCTURES
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * PROTOTYPES OF LOCAL FUNCTIONS
81 *----------------------------------------------------------------------------
86 IN OUT MEM_NB_BLOCK *NBPtr
90 *-----------------------------------------------------------------------------
93 *-----------------------------------------------------------------------------
95 STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm2D[] = {
96 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
97 {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
98 {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
99 {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
100 {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
101 {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
102 {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
103 {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
104 {DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
105 {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
108 STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
109 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
110 {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
111 {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
112 {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
113 {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
114 {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
115 {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
116 {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
118 /* -----------------------------------------------------------------------------*/
121 * This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
123 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
124 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
125 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
127 * @return AGESA_SUCCESS
132 MemPConstructPsRDr3 (
133 IN OUT MEM_DATA_STRUCT *MemPtr,
134 IN OUT CH_DEF_STRUCT *ChannelPtr,
135 IN OUT MEM_PS_BLOCK *PsPtr
138 ASSERT (MemPtr != 0);
139 ASSERT (ChannelPtr != 0);
142 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
143 return AGESA_UNSUPPORTED;
145 if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
146 return AGESA_UNSUPPORTED;
148 if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
149 return AGESA_UNSUPPORTED;
151 PsPtr->MemPDoPs = MemPDoPsRDr3;
152 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
153 return AGESA_SUCCESS;
156 /* -----------------------------------------------------------------------------*/
159 * This is function sets the platform specific settings for R-DDR3 DR DDR3
161 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
163 * @return TRUE - Find settings for corresponding platform and dimm population.
164 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
171 IN OUT MEM_NB_BLOCK *NBPtr
174 CONST DRAM_TERM_ENTRY *DramTermPtr;
175 UINT8 MaxDimmsPerChannel;
176 UINT8 *DimmsPerChPtr;
181 DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL);
182 if (DimmsPerChPtr != NULL) {
183 MaxDimmsPerChannel = *DimmsPerChPtr;
185 MaxDimmsPerChannel = 2;
188 if (MaxDimmsPerChannel == 2) {
189 DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm2D);
190 DramTermPtr = DrRDdr3DramTerm2D;
191 } else if (MaxDimmsPerChannel == 3) {
192 DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm3D);
193 DramTermPtr = DrRDdr3DramTerm3D;
198 if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {