7 * Platform specific settings for DA DDR3 U-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
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21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
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31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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42 * ***************************************************************************
46 /* This file contains routine that add platform specific support L1 */
50 #include "AdvancedApi.h"
54 #include "cpuFamRegisters.h"
59 #include "PlatformMemoryConfiguration.h"
60 #include "GeneralServices.h"
65 #define FILECODE PROC_MEM_PS_DA_MPUDA3_FILECODE
66 /*----------------------------------------------------------------------------
67 * DEFINITIONS AND MACROS
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * TYPEDEFS AND STRUCTURES
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * PROTOTYPES OF LOCAL FUNCTIONS
81 *----------------------------------------------------------------------------
86 IN OUT MEM_NB_BLOCK *NBPtr
91 MemPGetPORFreqLimitUDA3 (
92 IN OUT MEM_NB_BLOCK *NBPtr
95 *-----------------------------------------------------------------------------
98 *-----------------------------------------------------------------------------
100 STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
101 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
102 {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
103 {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
104 {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
106 /* -----------------------------------------------------------------------------*/
109 * This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
111 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
112 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
113 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
115 * @return AGESA_SUCCESS
120 MemPConstructPsUDA3 (
121 IN OUT MEM_DATA_STRUCT *MemPtr,
122 IN OUT CH_DEF_STRUCT *ChannelPtr,
123 IN OUT MEM_PS_BLOCK *PsPtr
126 ASSERT (MemPtr != 0);
127 ASSERT (ChannelPtr != 0);
129 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
130 return AGESA_UNSUPPORTED;
132 if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
133 return AGESA_UNSUPPORTED;
135 if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
136 return AGESA_UNSUPPORTED;
139 PsPtr->MemPDoPs = MemPDoPsUDA3;
140 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUDA3;
141 return AGESA_SUCCESS;
144 /* -----------------------------------------------------------------------------*/
147 * This is function sets the platform specific settings for U-DDR3 DA DDR3
149 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
151 * @return TRUE - Find settings for corresponding platform and dimm population.
152 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
159 IN OUT MEM_NB_BLOCK *NBPtr
162 if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
169 /* -----------------------------------------------------------------------------*/
172 * This is function gets the POR speed limit for U-DDR3 DA
174 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
180 MemPGetPORFreqLimitUDA3 (
181 IN OUT MEM_NB_BLOCK *NBPtr
186 if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
188 // Highest POR supported speed for Unbuffered dimm is 1333
190 SpeedLimit = DDR1333_FREQUENCY;
193 // Max LV DDR3 Speed is 1066 for this silicon
195 SpeedLimit = DDR1066_FREQUENCY;
198 if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
199 NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
200 } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
201 // Unbuffered DDR3 at 333MHz is not supported
202 NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
203 PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
204 SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
205 // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
206 NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;