7 * Platform specific settings for C32 DDR3 U-DIMM system
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
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21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
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29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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42 * ***************************************************************************
48 #include "AdvancedApi.h"
52 #include "cpuFamRegisters.h"
56 #include "PlatformMemoryConfiguration.h"
57 #include "GeneralServices.h"
62 #define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE
63 /*----------------------------------------------------------------------------
64 * DEFINITIONS AND MACROS
66 *----------------------------------------------------------------------------
68 #define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
70 /*----------------------------------------------------------------------------
71 * TYPEDEFS AND STRUCTURES
73 *----------------------------------------------------------------------------
76 /*----------------------------------------------------------------------------
77 * PROTOTYPES OF LOCAL FUNCTIONS
79 *----------------------------------------------------------------------------
84 IN OUT MEM_NB_BLOCK *NBPtr
89 MemPGetPORFreqLimitUC32_3 (
90 IN OUT MEM_NB_BLOCK *NBPtr
93 *-----------------------------------------------------------------------------
96 *-----------------------------------------------------------------------------
98 STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
99 {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
100 {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
101 {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
102 {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
105 /* -----------------------------------------------------------------------------*/
108 * This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
110 * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
111 * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
112 * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
114 * @return AGESA_SUCCESS
119 MemPConstructPsUC32_3 (
120 IN OUT MEM_DATA_STRUCT *MemPtr,
121 IN OUT CH_DEF_STRUCT *ChannelPtr,
122 IN OUT MEM_PS_BLOCK *PsPtr
125 ASSERT (MemPtr != 0);
126 ASSERT (ChannelPtr != 0);
128 if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
129 return AGESA_UNSUPPORTED;
131 if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
132 return AGESA_UNSUPPORTED;
134 if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
135 return AGESA_UNSUPPORTED;
137 PsPtr->MemPDoPs = MemPDoPsUC32_3;
138 PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3;
139 return AGESA_SUCCESS;
142 /* -----------------------------------------------------------------------------*/
145 * This is function sets the platform specific settings for U-DDR3 C32 DDR3
147 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
149 * @return TRUE - Find settings for corresponding platform and dimm population.
150 * @return FALSE - Fail to find settings for corresponding platform and dimm population.
157 IN OUT MEM_NB_BLOCK *NBPtr
160 if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) {
167 /* -----------------------------------------------------------------------------*/
170 * This is function gets the POR speed limit for SO-DDR3 C32
172 * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
178 MemPGetPORFreqLimitUC32_3 (
179 IN OUT MEM_NB_BLOCK *NBPtr
184 // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066
186 if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) {
187 MaxSpeed = DDR1066_FREQUENCY;
190 // Highest POR supported speed for Unbuffered dimm is 1333
192 MaxSpeed = DDR1333_FREQUENCY;
194 if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
195 NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
196 } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
197 // Unbuffered DDR3 at 333MHz is not supported
198 NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
199 PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
200 SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
201 // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
202 NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;