7 * Common Northbridge functions for Pharaoh Hound
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/NB/PH)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
46 *----------------------------------------------------------------------------
49 *----------------------------------------------------------------------------
55 #include "AdvancedApi.h"
58 #include "OptionMemory.h"
65 #include "cpuRegisters.h"
66 #include "cpuFamRegisters.h"
67 #include "cpuFamilyTranslation.h"
68 #include "heapManager.h"
69 #include "GeneralServices.h"
74 #define FILECODE PROC_MEM_NB_PH_MNPH_FILECODE
77 /*----------------------------------------------------------------------------
78 * DEFINITIONS AND MACROS
80 *----------------------------------------------------------------------------
83 #define SPLIT_CHANNEL (UINT32) 0x20000000
84 #define CHANNEL_SELECT (UINT32) 0x10000000
86 /*----------------------------------------------------------------------------
87 * TYPEDEFS AND STRUCTURES
89 *----------------------------------------------------------------------------
92 /*----------------------------------------------------------------------------
93 * PROTOTYPES OF LOCAL FUNCTIONS
95 *----------------------------------------------------------------------------
98 /*----------------------------------------------------------------------------
101 *----------------------------------------------------------------------------
104 extern BUILD_OPT_CFG UserOptions;
105 extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
107 /* -----------------------------------------------------------------------------*/
111 * This function initializes the northbridge block
113 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
114 * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
115 * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
116 * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
117 * @param[in] NodeID - UINT8 indicating node ID of the NB object.
119 * @return Boolean indicating that this is the correct memory
120 * controller type for the node number that was passed in.
124 MemConstructNBBlockPh (
125 IN OUT MEM_NB_BLOCK *NBPtr,
126 IN OUT MEM_DATA_STRUCT *MemPtr,
127 IN MEM_FEAT_BLOCK_NB *FeatPtr,
128 IN MEM_SHARED_DATA *SharedPtr,
134 UINT8 SpdSocketIndex;
135 UINT8 SpdChannelIndex;
137 ALLOCATE_HEAP_PARAMS AllocHeapParams;
140 // Determine if this is the expected NB Type
142 GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
143 if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
147 NBPtr->MemPtr = MemPtr;
148 NBPtr->RefPtr = MemPtr->ParameterListPtr;
149 NBPtr->SharedPtr = SharedPtr;
151 MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
152 NBPtr->MCTPtr = MCTPtr;
153 NBPtr->MCTPtr->NodeId = NodeID;
154 NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
155 NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
158 // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
160 AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
161 sizeof (DCT_STRUCT) + (
162 MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
165 AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
166 AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
167 if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
168 PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
169 SetMemError (AGESA_FATAL, MCTPtr);
173 MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
174 MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
175 AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
176 for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
177 MCTPtr->DctData[Dct].Dct = Dct;
178 MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
179 MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
180 MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
181 AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
183 NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
186 // Initialize Socket List
188 for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
189 MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
190 MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
191 MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
194 MemNInitNBDataPh (NBPtr);
196 FeatPtr->InitCPG (NBPtr);
197 NBPtr->FeatPtr = FeatPtr;
198 FeatPtr->InitHwRxEn (NBPtr);
201 // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
202 // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
203 // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
204 // dimm types(QR or not) are known. This is done in the Technology block constructor.
206 // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
207 // This will facilitate modifications due to some processors that might
208 // map the DCT-CHANNEL differently.
210 SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
212 // Traverse the Dct/Channel structures
214 for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
215 for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
217 // Calculate the number of Dimms on this channel using the
218 // die/dct/channel to Socket/channel conversion.
220 SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
221 NBPtr->MCTPtr->SocketId,
222 MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
224 NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
228 MemNSwitchDCTNb (NBPtr, 0);
232 /* -----------------------------------------------------------------------------*/
235 * This function initializes member functions and variables of NB block.
237 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
243 IN OUT MEM_NB_BLOCK *NBPtr
248 NBPtr->DctCachePtr = NBPtr->DctCache;
249 NBPtr->PsPtr = NBPtr->PSBlock;
251 InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
252 NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
255 NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
256 NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
257 NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
258 NBPtr->Ganged = FALSE;
259 NBPtr->PosTrnPattern = POS_PATTERN_72B;
260 NBPtr->MemCleared = FALSE;
261 NBPtr->StartupSpeed = DDR800_FREQUENCY;
262 NBPtr->RcvrEnDlyLimit = 0xFF;
263 NBPtr->DefDctSelIntLvAddr = 3;
264 NBPtr->CsRegMsk = 0x1FF83FE0;
266 for (i = 0; i < EnumSize; i++) {
267 NBPtr->IsSupported[i] = FALSE;
270 LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
272 NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
273 NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
274 NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
275 NBPtr->InitializeMCT = MemNInitializeMctDA;
276 NBPtr->FinalizeMCT = MemNFinalizeMctPh;
277 NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
278 NBPtr->sendZQCmd = MemNSendZQCmdNb;
279 NBPtr->WritePattern = MemNWritePatternDA;
280 NBPtr->ReadPattern = MemNReadPatternDA;
281 NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
282 NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
283 NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
284 NBPtr->StitchMemory = MemNStitchMemoryNb;
285 NBPtr->AutoConfig = memNAutoConfigDA;
286 NBPtr->PlatformSpec = MemNPlatformSpecNb;
287 NBPtr->InitMCT = MemNInitMCTNb;
288 NBPtr->DisableDCT = MemNDisableDCTNb;
289 NBPtr->StartupDCT = MemNStartupDCTNb;
290 NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
291 NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
292 NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
293 NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
294 NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
295 NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
296 NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
297 NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
298 NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
299 NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
300 NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
301 NBPtr->OtherTiming = MemNOtherTimingDA;
302 NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
303 NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
304 NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
305 NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
306 NBPtr->TrainingFlow = MemNTrainingFlowNb;
307 NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
308 MemNInitNBDataNb (NBPtr);
309 NBPtr->PollBitField = MemNPollBitFieldNb;
310 NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
311 NBPtr->BrdcstSet = MemNBrdcstSetNb;
312 NBPtr->GetTrainDly = MemNGetTrainDlyNb;
313 NBPtr->SetTrainDly = MemNSetTrainDlyNb;
314 NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
315 NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
316 NBPtr->RankEnabled = MemNRankEnabledNb;
317 NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
318 NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitPh;
319 NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
320 NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
321 NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
322 NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
323 NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
324 NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
325 NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet;
326 NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
327 NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
328 NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
329 NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
330 NBPtr->CSPerChannel = MemNCSPerChannelNb;
331 NBPtr->CSPerDelay = MemNCSPerDelayNb;
332 NBPtr->FlushPattern = MemNFlushPatternNb;
333 NBPtr->GetUmaSize = MemNGetUmaSizeNb;
334 NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
335 NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
336 NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
337 NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
338 NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
339 NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
340 NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
341 NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
342 NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
343 NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
344 NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
346 NBPtr->IsSupported[SetSpareEn] = TRUE;
347 NBPtr->IsSupported[CheckSpareEn] = TRUE;
348 NBPtr->IsSupported[SetDllShutDown] = TRUE;
349 NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
350 NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
351 NBPtr->IsSupported[Check1GAlign] = TRUE;
352 NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
353 NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
354 NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
355 NBPtr->IsSupported[CheckFindPSDct] = TRUE;
356 NBPtr->IsSupported[CheckDllStdBy] = TRUE;
357 NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
358 NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
359 NBPtr->IsSupported[CheckDllRegDis] = TRUE;
360 NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
363 /* -----------------------------------------------------------------------------*/
367 * This function initializes the default values in the MEM_DATA_STRUCT
369 * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
374 IN OUT MEM_DATA_STRUCT *MemPtr
379 MEM_PARAMETER_STRUCT *RefPtr;
380 ASSERT (MemPtr != NULL);
381 RefPtr = MemPtr->ParameterListPtr;
384 // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
385 RefPtr->BottomIo = 0xE0;
386 RefPtr->UmaMode = UserOptions.CfgUmaMode;
387 RefPtr->UmaSize = UserOptions.CfgUmaSize;
388 RefPtr->MemHoleRemapping = TRUE;
389 RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
392 RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
393 RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
394 for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
395 for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
396 MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
397 MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
402 RefPtr->EnableMemClr = TRUE;
404 // TableBasedAlterations
405 RefPtr->TableBasedAlterations = NULL;
407 // Platform config table
408 RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
411 RefPtr->MemRestoreCtl = FALSE;
412 RefPtr->SaveMemContextCtl = FALSE;
413 AmdS3ParamsInitializer (&RefPtr->MemContext);
415 // Dram Configuration
416 RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
417 RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
418 RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
419 RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
420 RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
421 RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
424 RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
427 RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
430 RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature;
433 RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
436 /*-----------------------------------------------------------------------------*/
439 * This function writes training pattern
440 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
441 * @param[in] Pattern[] - Pattern to write
442 * @param[in] Address - System Address [47:16]
443 * @param[in] ClCount - Number of cache lines
449 IN OUT MEM_NB_BLOCK *NBPtr,
455 Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
456 MemUWriteCachelines (Address, Pattern, ClCount);
459 /*-----------------------------------------------------------------------------*/
462 * This function reads training pattern
463 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
464 * @param[in] Buffer[] - Buffer to fill
465 * @param[in] Address - System Address [47:16]
466 * @param[in] ClCount - Number of cache lines
472 IN OUT MEM_NB_BLOCK *NBPtr,
478 Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
479 MemUReadCachelines (Buffer, Address, ClCount);
482 /* -----------------------------------------------------------------------------*/
485 * This function initiates DQS training for Server NB
487 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
492 memNEnableTrainSequencePh (
493 IN OUT MEM_NB_BLOCK *NBPtr
498 if (!MemNIsIdSupportedPh (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {