1 ;*****************************************************************************
2 ; AMD Generic Encapsulated Software Architecture
4 ; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
5 ; Description: Main memory controller system configuration for AGESA
8 ;*****************************************************************************
10 ; Copyright (C) 2012 Advanced Micro Devices, Inc.
11 ; All rights reserved.
13 ; Redistribution and use in source and binary forms, with or without
14 ; modification, are permitted provided that the following conditions are met:
15 ; * Redistributions of source code must retain the above copyright
16 ; notice, this list of conditions and the following disclaimer.
17 ; * Redistributions in binary form must reproduce the above copyright
18 ; notice, this list of conditions and the following disclaimer in the
19 ; documentation and/or other materials provided with the distribution.
20 ; * Neither the name of Advanced Micro Devices, Inc. nor the names of
21 ; its contributors may be used to endorse or promote products derived
22 ; from this software without specific prior written permission.
24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 ; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 ; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
28 ; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 ; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 ; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 ; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 ; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ;*****************************************************************************
36 ;============================================================================
47 ; Define the calling convention used for the C library modules
48 ;@attention - This should be in a central include file
52 ;===============================================================================
55 ; Do a 32 Bit IO Out operation using edx.
56 ; NOTE: This function will be obsolete in the future.
58 ; In: Port - port number
59 ; Value - value to be written
63 ; All registers preserved.
64 ;===============================================================================
65 MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
75 ;----------------------------------------------------------------------------
82 ;----------------------------------------------------------------------------
89 ;----------------------------------------------------------------------------
93 out 0EDh,al ;prevent speculative execution of following instructions
96 ;===============================================================================
98 ; Write a test pattern to DRAM
100 ; In: Pattern - pointer to the write pattern
101 ; Address - Physical address to be read
102 ; ClCount - number of cachelines to be read
105 ;All registers preserved.
106 ;===============================================================================
107 MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
115 mov edx, DWORD PTR Pattern
123 db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
124 db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
132 MemUWriteCachelines ENDP
134 ;===============================================================================
137 ; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
138 ;pattern is a stress pattern which exercises both ISI and crosstalk. The number
139 ;of cache lines to fill is dependent on DCT width mode and burstlength.
141 ; In: Buffer - pointer to a buffer where read data will be stored
142 ; Address - Physical address to be read
143 ; ClCount - number of cachelines to be read
146 ;All registers preserved.
147 ;===============================================================================
148 MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
151 ; First, issue continuous dummy reads to fill up the cache
160 add edi,128 ;bias value (to account for signed displacement)
161 ;clflush opcode=0F AE /7
166 add edi,4*64 ;TestAddr+4 cache lines
167 add ebx,8*64 ;TestAddr+8 cache lines
168 add ecx,12*64 ;TestAddr+12 cache lines
169 add edx,16*64 ;TestAddr+16 cache lines
172 mov eax,fs:[esi-128] ;TestAddr
174 mov eax,fs:[esi-64] ;TestAddr+1 cache line
176 mov eax,fs:[esi] ;TestAddr+2 cache lines
178 mov eax,fs:[esi+64] ;TestAddr+3 cache lines
180 mov eax,fs:[edi-128] ;TestAddr+4 cache lines
182 mov eax,fs:[edi-64] ;TestAddr+5 cache lines
184 mov eax,fs:[edi] ;TestAddr+6 cache lines
186 mov eax,fs:[edi+64] ;TestAddr+7 cache lines
188 mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
190 mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
192 mov eax,fs:[ebx] ;TestAddr+10 cache lines
194 mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
196 mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
198 mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
200 mov eax,fs:[ecx] ;TestAddr+14 cache lines
202 mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
205 add eax,(16*64) ;Next 16CL
210 add edi,128 ;bias value (to account for signed displacement)
211 ;clflush opcode=0F AE /7
216 add edi,4*64 ;TestAddr+4 cache lines
217 add ebx,8*64 ;TestAddr+8 cache lines
218 add ecx,12*64 ;TestAddr+12 cache lines
219 add edx,16*64 ;TestAddr+16 cache lines
223 mov eax,fs:[esi-128] ;TestAddr
225 .elseif(ClCount == 3)
227 mov eax,fs:[esi-128] ;TestAddr
229 mov eax,fs:[esi-64] ;TestAddr+1 cache line
231 mov eax,fs:[esi] ;TestAddr+2 cache lines
233 .elseif(ClCount == 6)
235 mov eax,fs:[esi-128] ;TestAddr
237 mov eax,fs:[esi-64] ;TestAddr+1 cache line
239 mov eax,fs:[esi] ;TestAddr+2 cache lines
241 mov eax,fs:[esi+64] ;TestAddr+3 cache lines
243 mov eax,fs:[edi-128] ;TestAddr+4 cache lines
245 mov eax,fs:[edi-64] ;TestAddr+5 cache lines
247 .elseif(ClCount == 9)
249 mov eax,fs:[esi-128] ;TestAddr
251 mov eax,fs:[esi-64] ;TestAddr+1 cache line
253 mov eax,fs:[esi] ;TestAddr+2 cache lines
255 mov eax,fs:[esi+64] ;TestAddr+3 cache lines
257 mov eax,fs:[edi-128] ;TestAddr+4 cache lines
259 mov eax,fs:[edi-64] ;TestAddr+5 cache lines
261 mov eax,fs:[edi] ;TestAddr+6 cache lines
263 mov eax,fs:[edi+64] ;TestAddr+7 cache lines
265 mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
267 .elseif(ClCount == 18)
269 mov eax,fs:[esi-128] ;TestAddr
271 mov eax,fs:[esi-64] ;TestAddr+1 cache line
273 mov eax,fs:[esi] ;TestAddr+2 cache lines
275 mov eax,fs:[esi+64] ;TestAddr+3 cache lines
277 mov eax,fs:[edi-128] ;TestAddr+4 cache lines
279 mov eax,fs:[edi-64] ;TestAddr+5 cache lines
281 mov eax,fs:[edi] ;TestAddr+6 cache lines
283 mov eax,fs:[edi+64] ;TestAddr+7 cache lines
285 mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
287 mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
289 mov eax,fs:[ebx] ;TestAddr+10 cache lines
291 mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
293 mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
295 mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
297 mov eax,fs:[ecx] ;TestAddr+14 cache lines
299 mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
301 mov eax,fs:[edx] ;TestAddr+16 cache lines
303 mov eax,fs:[edx+64] ;TestAddr+17 cache lines
309 ; Then, copy data to buffer
312 mov edx,DWORD PTR Buffer
326 MemUReadCachelines ENDP
328 ;===============================================================================
331 ; Perform a single cache line read from a given physical address.
333 ; In: Address - Physical address to be read
334 ; ClCount - number of cachelines to be read
337 ;All registers preserved.
338 ;===============================================================================
339 MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
348 ;===============================================================================
351 ; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
352 ;to ensure cache miss on the next read training.
354 ; In: Address - Physical address to be flushed
355 ; ClCount - number of cachelines to be flushed
358 ;All registers preserved.
359 ;===============================================================================
360 MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
365 _MFENCE ; Force strong ordering of clflush
366 db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
372 MemUFlushPattern ENDP
375 ;===============================================================================
377 ; Read ClCount number of cachelines then return the bitmap that indicates
378 ; the write leveling result of each byte lane.
380 ; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
381 ; Address - Physical address to be sampled
382 ; ClCount - number of cachelines to be read
384 ; OUT: ErrBitmap - WL result
386 ;All registers preserved
387 ;===============================================================================
388 MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
389 LOCAL ZeroCount[32]:WORD
402 ; Then, count the number of 0's
407 mov cx,SIZEOF ZeroCount
418 test al,00Fh ;check lower nibble
423 test al,0F0h ;check upper nibble
438 ; Then, average and compress data to error bits
446 .if(WORD PTR [esi] < dx)
453 mov dx,WORD PTR ErrBitmap
458 MemUGetWrLvNblErr ENDP
460 ;===============================================================================
461 ;AlignPointerTo16Byte:
462 ; Modifies BufferPtr to be 16 byte aligned
464 ; In: BufferPtrPtr - Pointer to buffer pointer
465 ; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
467 ;All registers preserved.
468 ;===============================================================================
469 AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
472 mov edx, BufferPtrPtr
480 AlignPointerTo16Byte ENDP
482 ;===============================================================================
484 ; Serialize instruction
489 ;All registers preserved.
490 ;===============================================================================
491 MemUMFenceInstr PROC CALLCONV PUBLIC