7 * Main Memory Feature implementation file for Standard Training
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Main)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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21 * modification, are permitted provided that the following conditions are met:
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42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
57 #include "cpuRegisters.h"
58 #include "cpuServices.h"
59 #include "OptionMemory.h"
68 #define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE
71 /*----------------------------------------------------------------------------
72 * PROTOTYPES OF LOCAL FUNCTIONS
74 *----------------------------------------------------------------------------
78 MemMStandardTraining (
79 IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
83 MemMStandardTrainingUsingAdjacentDies (
84 IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
87 /*-----------------------------------------------------------------------------
90 *-----------------------------------------------------------------------------
92 extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
93 /* -----------------------------------------------------------------------------*/
96 * MemMStandardTraining
98 * This function implements standard memory training whereby training functions
99 * for all nodes are run by the BSP.
102 * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
104 * @return TRUE - No fatal error occurs.
105 * @return FALSE - Fatal error occurs.
108 MemMStandardTraining (
109 IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
114 // Run Northbridge-specific Standard Training feature for each die.
116 IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n");
117 for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
118 IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die);
119 AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
120 mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);
121 mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = TRUE;
122 mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);
123 mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL);
124 mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);
125 if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
129 return (BOOLEAN) (Die == mmPtr->DieCount);
132 /* -----------------------------------------------------------------------------*/
135 * MemMStandardTrainingUsingAdjacentDies
137 * This function implements standard memory training whereby training functions
138 * for all nodes are run by the BSP while enabling other dies to eable argressor channel
141 * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
143 * @return TRUE - No fatal error occurs.
144 * @return FALSE - Fatal error occurs.
147 MemMStandardTrainingUsingAdjacentDies (
148 IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
153 UINT32 AdjacentSocketNum;
154 UINT32 TargetSocketNum;
159 BOOLEAN FirstCsFound;
161 // Run Northbridge-specific Standard Training feature for each die.
163 IDS_HDT_CONSOLE (MEM_STATUS, "\nStart standard serial training\n");
164 for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
165 IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die);
166 AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
167 mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);
168 mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = FALSE;
169 mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);
170 if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
174 IDS_HDT_CONSOLE (MEM_STATUS, "\nStart training with agressors\n");
175 for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
176 IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die);
177 AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
178 GetSocketModuleOfNode (Die, &TargetSocketNum, &ModuleNum, &(mmPtr->MemPtr->StdHeader));
179 for (AdjacentDie = 0; AdjacentDie < mmPtr->DieCount; AdjacentDie++) {
180 mmPtr->NBPtr[Die].DieEnabled[AdjacentDie] = FALSE;
181 GetSocketModuleOfNode (AdjacentDie, &AdjacentSocketNum, &ModuleNum, &(mmPtr->MemPtr->StdHeader));
182 if (TargetSocketNum == AdjacentSocketNum) {
183 if (AdjacentDie != Die) {
184 if (mmPtr->NBPtr[AdjacentDie].MCTPtr->NodeMemSize != 0) {
185 mmPtr->NBPtr[Die].AdjacentDieNBPtr = &mmPtr->NBPtr[AdjacentDie];
186 mmPtr->NBPtr[Die].DieEnabled[AdjacentDie] = TRUE;
189 if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) {
190 mmPtr->NBPtr[Die].DieEnabled[Die] = TRUE;
193 // Determine the initial target CS, Max Dimms and max CS number for all DCTs (potential aggressors)
194 if (mmPtr->NBPtr[AdjacentDie].MCTPtr->NodeMemSize != 0) {
195 for (Dct = 0; Dct < mmPtr->NBPtr[AdjacentDie].DctCount; Dct++) {
196 FirstCsFound = FALSE;
197 mmPtr->NBPtr[AdjacentDie].SwitchDCT (&mmPtr->NBPtr[AdjacentDie], Dct);
198 for (ChipSel = 0; ChipSel < mmPtr->NBPtr[AdjacentDie].CSPerChannel (&mmPtr->NBPtr[AdjacentDie]); ChipSel = ChipSel + mmPtr->NBPtr[AdjacentDie].CSPerDelay (&mmPtr->NBPtr[AdjacentDie]) ) {
199 if ((mmPtr->NBPtr[AdjacentDie].DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) {
200 if (FirstCsFound == FALSE) {
201 // Set Initial CS value for Current Aggressor CS
202 mmPtr->NBPtr[AdjacentDie].InitialAggressorCSTarget[Dct] = ChipSel;
203 mmPtr->NBPtr[AdjacentDie].CurrentAggressorCSTarget[Dct] = mmPtr->NBPtr[AdjacentDie].InitialAggressorCSTarget[Dct];
206 mmPtr->NBPtr[AdjacentDie].MaxAggressorCSEnabled[Dct] = ChipSel;
207 mmPtr->NBPtr[AdjacentDie].MaxAggressorDimms[Dct]++;
214 if (mmPtr->NBPtr[Die].MCTPtr->NodeMemSize != 0) {
215 //Execute Technology specific training features
217 while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) {
218 if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (&mmPtr->NBPtr[Die])) {
219 mmPtr->NBPtr[Die].TrainingSequenceIndex = i;
220 // Execute RdDqs Training
221 memTrainSequenceDDR3[i].MemTechFeatBlock->RdDqs__Training (mmPtr->NBPtr[Die].TechPtr);
222 // Execute MaxRdLat Training After training
224 if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (mmPtr->NBPtr[Die].TechPtr)) {
225 MemFInitTableDrive (&mmPtr->NBPtr[Die], MTAfterMaxRdLatTrn);
227 } while (mmPtr->NBPtr->ChangeNbFrequency (&mmPtr->NBPtr[Die]));
233 mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL);
234 mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);
235 if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
239 return (BOOLEAN) (Die == mmPtr->DieCount);