7 * Main Memory Feature implementation file for low voltage DDR3 support
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Main)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
57 #include "OptionMemory.h"
61 #include "GeneralServices.h"
66 #define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE
68 extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
69 /*----------------------------------------------------------------------------
70 * PROTOTYPES OF LOCAL FUNCTIONS
72 *----------------------------------------------------------------------------
75 /*-----------------------------------------------------------------------------
78 *-----------------------------------------------------------------------------
81 /* -----------------------------------------------------------------------------*/
84 * Find the common supported voltage on all nodes.
86 * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
88 * @return TRUE - No fatal error occurs.
89 * @return FALSE - Fatal error occurs.
93 IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
100 MEM_PARAMETER_STRUCT *ParameterPtr;
101 MEM_SHARED_DATA *mmSharedPtr;
103 NBPtr = MemMainPtr->NBPtr;
104 mmSharedPtr = MemMainPtr->mmSharedPtr;
105 ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
106 mmSharedPtr->VoltageMap = 0xFF;
110 for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
111 NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]);
112 // Check if there is no common supported voltage
113 if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) {
114 // restart node loop by setting node to 0xFF
120 if (mmSharedPtr->VoltageMap == 0) {
121 IDS_HDT_CONSOLE (MEM_FLOW, "\nNo commonly supported VDDIO is found.\n");
122 PutEventLog (AGESA_WARNING, MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader));
123 SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr);
124 // When there is no commonly supported VDDIO, use 1.35V as the temporal VDDIO
125 ParameterPtr->DDR3Voltage = VOLT1_35;
127 IDS_HDT_CONSOLE (MEM_FLOW, "\nCommonly supported VDDIO is: %s%s%s.\n", ((mmSharedPtr->VoltageMap & 1) != 0) ? "1.5V, " : "", ((mmSharedPtr->VoltageMap & 2) != 0) ? "1.35V, " : "", ((mmSharedPtr->VoltageMap & 4) != 0) ? "1.25V" : "");
128 ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (LibAmdBitScanReverse (mmSharedPtr->VoltageMap));
131 for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
132 // Check if the voltage needs force to 1.5V
133 NBPtr[Node].FamilySpecificHook[ForceLvDimmVoltage] (&NBPtr[Node], MemMainPtr);
135 RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
141 /* -----------------------------------------------------------------------------*/
144 * Find the common supported voltage on all nodes, taken into account of the
145 * user option for performance and power saving.
147 * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
149 * @return TRUE - No fatal error occurs.
150 * @return FALSE - Fatal error occurs.
153 MemMLvDdr3PerformanceEnhPre (
154 IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
161 MEM_PARAMETER_STRUCT *ParameterPtr;
162 MEM_SHARED_DATA *mmSharedPtr;
163 PLATFORM_POWER_POLICY PowerPolicy;
165 NBPtr = MemMainPtr->NBPtr;
166 mmSharedPtr = MemMainPtr->mmSharedPtr;
167 ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
168 PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;
170 IDS_OPTION_HOOK (IDS_MEMORY_POWER_POLICY, &PowerPolicy, &NBPtr->MemPtr->StdHeader);
171 IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "\nMaximize Performance\n" : "\nMaximize Battery Life\n");
173 if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) {
174 mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
175 PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader));
176 SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr);
177 IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed.\n");
180 RetVal = MemMLvDdr3 (MemMainPtr);
182 VDDIO = ParameterPtr->DDR3Voltage;
183 if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) {
184 // When there is no commonly supported voltage, do not optimize performance
185 // For cases where we can maximize performance, do the following
186 // When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO
187 // So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance.
188 ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
191 IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);
193 if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {
194 // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance
195 mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
196 IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done.\n");
198 for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
199 NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
200 NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
201 NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;
203 // Reprogram the leveling result as temporal candidate
204 ParameterPtr->DDR3Voltage = VDDIO;
208 ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED);
212 /* -----------------------------------------------------------------------------*/
215 * Finalize the VDDIO for the board for performance enhancement.
217 * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
219 * @return TRUE - No fatal error occurs.
220 * @return FALSE - Fatal error occurs.
223 MemMLvDdr3PerformanceEnhFinalize (
224 IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
229 UINT8 NodeCnt[VOLT1_25 + 1];
232 MEM_PARAMETER_STRUCT *ParameterPtr;
233 MEM_SHARED_DATA *mmSharedPtr;
234 UINT8 CurrentVoltage;
235 DIMM_VOLTAGE Voltage;
236 MEMORY_BUS_SPEED HighestFreq;
238 ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
239 mmSharedPtr = MemMainPtr->mmSharedPtr;
240 NBPtr = MemMainPtr->NBPtr;
242 LibAmdMemFill (NodeCnt, 0, VOLT1_25_ENCODED_VAL + 1, &NBPtr->MemPtr->StdHeader);
243 if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
244 Voltage = ParameterPtr->DDR3Voltage;
245 IDS_HDT_CONSOLE (MEM_FLOW, "\nSearching for VDDIO that can maximize frequency: \n");
246 for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
248 // Find out what the highest frequency that can be reached is on this node across different voltage.
249 for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
250 if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) {
251 HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage];
254 IDS_HDT_CONSOLE (MEM_FLOW, "Node%d: 1.5V -> %dMHz, 1.35V -> %dMHz, 1.25V -> %dMHz\n", Node, NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL], NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL]);
255 // Figure out what voltage we can have when attaining the highest frequency.
256 for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
257 if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) {
258 NodeCnt[CurrentVoltage] ++;
262 IDS_HDT_CONSOLE (MEM_FLOW, "Number of nodes that can run at maximize performance: 1.5V -> %d Nodes 1.35V -> %d Nodes 1.25V -> %d Nodes.\n", NodeCnt[VOLT1_5_ENCODED_VAL], NodeCnt[VOLT1_35_ENCODED_VAL], NodeCnt[VOLT1_25_ENCODED_VAL]);
264 // Use the VDDIO at which most nodes can run at higher frequency
265 for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
266 if (MaxCnt <= NodeCnt[CurrentVoltage]) {
267 MaxCnt = NodeCnt[CurrentVoltage];
268 ParameterPtr->DDR3Voltage = CONVERT_ENCODED_TO_VDDIO (CurrentVoltage);
272 ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED);
274 mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
275 if (Voltage != ParameterPtr->DDR3Voltage) {
276 // Finalize frequency with updated finalized VDDIO
277 for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
278 // Need to re-sync target speed and different VDDIO may cause different settings
279 NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr);
280 for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) {
281 NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct);
282 if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) {
283 if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) {