7 * Main Memory initialization sequence for DR
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Main/DR)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
57 #include "OptionMemory.h"
62 #include "cpuFamilyTranslation.h"
64 #include "GeneralServices.h"
68 #define FILECODE PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE
72 extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
74 /*----------------------------------------------------------------------------
75 * DEFINITIONS AND MACROS
77 *----------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------
81 * TYPEDEFS AND STRUCTURES
83 *----------------------------------------------------------------------------
86 /*----------------------------------------------------------------------------
87 * PROTOTYPES OF LOCAL FUNCTIONS
89 *----------------------------------------------------------------------------
92 /*----------------------------------------------------------------------------
95 *----------------------------------------------------------------------------
97 /* -----------------------------------------------------------------------------*/
101 * This function defines the memory initialization flow for
102 * systems that only support RB processors.
104 * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
106 * @return AGESA_STATUS
114 IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
120 MEM_TECH_BLOCK *TechPtr;
121 MEM_DATA_STRUCT *MemPtr;
123 NBPtr = MemMainPtr->NBPtr;
124 TechPtr = MemMainPtr->TechPtr;
125 NodeCnt = MemMainPtr->DieCount;
126 MemPtr = MemMainPtr->MemPtr;
128 GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
129 if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
130 MemPtr->IsFlowControlSupported = FALSE;
133 MemPtr->IsFlowControlSupported = TRUE;
136 for (Node = 0; Node < NodeCnt; Node++) {
137 MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
140 //----------------------------------------------------------------
142 //----------------------------------------------------------------
143 AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
144 for (Node = 0; Node < NodeCnt; Node++) {
145 if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
150 //----------------------------------------------------------------
152 //----------------------------------------------------------------
153 // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
154 AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
155 if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
159 //----------------------------------------------------------------
160 // Initialize DRAM and DCTs, and Create Memory Map
161 //----------------------------------------------------------------
162 AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
163 for (Node = 0; Node < NodeCnt; Node++) {
164 // Initialize Memory Controller and Dram
165 IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
167 if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
168 return AGESA_FATAL; //fatalexit
172 AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
173 if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
178 //----------------------------------------------------
179 // If there is no dimm on the system, do fatal exit
180 //----------------------------------------------------
181 if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
182 PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
187 //----------------------------------------------------------------
189 //----------------------------------------------------------------
190 AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
191 for (Node = 0; Node < NodeCnt; Node++) {
192 if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
197 //----------------------------------------------------------------
199 //----------------------------------------------------------------
200 AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
201 if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
205 //----------------------------------------------------------------
206 // Before Training Table values
207 //----------------------------------------------------------------
208 for (Node = 0; Node < NodeCnt; Node++) {
209 MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
212 //----------------------------------------------------------------
213 // Memory Context Restore
214 //----------------------------------------------------------------
215 if (!MemFeatMain.MemRestore (MemMainPtr)) {
216 // Do DQS training only if memory context restore fails
218 //----------------------------------------------------------------
220 //----------------------------------------------------------------
221 AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
222 MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
223 IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
224 if (!MemFeatMain.Training (MemMainPtr)) {
228 IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
231 //----------------------------------------------------------------
232 // Disable chipselects that fail training
233 //----------------------------------------------------------------
234 MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
235 MemFeatMain.ExcludeDIMM (MemMainPtr);
236 MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
238 //----------------------------------------------------------------
240 //----------------------------------------------------------------
241 AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
242 for (Node = 0; Node < NodeCnt; Node++) {
243 if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
248 //----------------------------------------------------------------
249 // After Training Table values
250 //----------------------------------------------------------------
251 for (Node = 0; Node < NodeCnt; Node++) {
252 MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
255 //----------------------------------------------------------------
257 //----------------------------------------------------------------
258 AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
259 for (Node = 0; Node < NodeCnt; Node++) {
260 if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
265 //----------------------------------------------------------------
267 //----------------------------------------------------------------
268 if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
272 //----------------------------------------------------------------
274 //----------------------------------------------------------------
275 for (Node = 0; Node < NodeCnt; Node++) {
276 if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
277 if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
283 //----------------------------------------------------------------
285 //----------------------------------------------------------------
286 if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
290 //----------------------------------------------------------------
291 // Interleave channels
292 //----------------------------------------------------------------
293 for (Node = 0; Node < NodeCnt; Node++) {
294 if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
295 if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
301 //----------------------------------------------------------------
302 // After Programming Interleave registers
303 //----------------------------------------------------------------
304 for (Node = 0; Node < NodeCnt; Node++) {
305 MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
308 //----------------------------------------------------------------
309 // UMA Allocation & UMAMemTyping
310 //----------------------------------------------------------------
311 AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
312 if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
317 //----------------------------------------------------------------
318 if (!MemFeatMain.InitEcc (MemMainPtr)) {
322 //----------------------------------------------------------------
324 //----------------------------------------------------------------
325 AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
326 if (!MemFeatMain.MemClr (MemMainPtr)) {
330 //----------------------------------------------------------------
332 //----------------------------------------------------------------
333 for (Node = 0; Node < NodeCnt; Node++) {
334 if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
335 if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
341 //----------------------------------------------------------------
343 //----------------------------------------------------------------
344 for (Node = 0; Node < NodeCnt; Node++) {
345 if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
350 //----------------------------------------------------------------
351 // After Finalize MCT
352 //----------------------------------------------------------------
353 for (Node = 0; Node < NodeCnt; Node++) {
354 MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
357 //----------------------------------------------------------------
358 // Memory Context Save
359 //----------------------------------------------------------------
360 MemFeatMain.MemSave (MemMainPtr);
362 //----------------------------------------------------------------
363 // Memory DMI support
364 //----------------------------------------------------------------
365 if (!MemFeatMain.MemDmi (MemMainPtr)) {
366 return AGESA_CRITICAL;
369 return AGESA_SUCCESS;
372 /*----------------------------------------------------------------------------
375 *----------------------------------------------------------------------------