7 * Feature Region interleaving support
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Feat/Intlvrgn)
12 * @e \$Revision: 49831 $ @e \$Date: 2011-03-29 10:26:15 -0600 (Tue, 29 Mar 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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21 * modification, are permitted provided that the following conditions are met:
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26 * documentation and/or other materials provided with the distribution.
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42 * ***************************************************************************
48 *----------------------------------------------------------------------------
51 *----------------------------------------------------------------------------
58 #include "heapManager.h"
62 #include "mfintlvrn.h"
68 #define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE
69 /*----------------------------------------------------------------------------
70 * DEFINITIONS AND MACROS
72 *----------------------------------------------------------------------------
74 #define _4GB_RJ27 ((UINT32)4 << (30 - 27))
75 /*----------------------------------------------------------------------------
76 * TYPEDEFS AND STRUCTURES
78 *----------------------------------------------------------------------------
81 /*----------------------------------------------------------------------------
82 * PROTOTYPES OF LOCAL FUNCTIONS
84 *----------------------------------------------------------------------------
87 /*----------------------------------------------------------------------------
90 *----------------------------------------------------------------------------
93 /* -----------------------------------------------------------------------------*/
96 * MemFInterleaveRegion:
98 * Applies region interleaving if both DCTs have different size of memory, and
99 * the channel interleaving region doesn't have UMA covered.
101 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
106 MemFInterleaveRegion (
107 IN OUT MEM_NB_BLOCK *NBPtr
116 LOCATE_HEAP_PTR LocHeap;
117 UMA_INFO *UmaInfoPtr;
119 MEM_DATA_STRUCT *MemPtr;
120 MEM_PARAMETER_STRUCT *RefPtr;
123 MemPtr = NBPtr->MemPtr;
124 RefPtr = NBPtr->RefPtr;
125 MCTPtr = NBPtr->MCTPtr;
127 UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16);
129 //TOM scaled from [47:0] to [47:27]
130 LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
131 SMsr.lo += (16 << 20); // Add 16MB to gain back C6 region if C6 is enabled
132 TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
134 //TOM2 scaled from [47:0] to [47:27]
135 LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
136 TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
138 TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM;
141 //Check if channel interleaving is enabled ? if so, go to next step.
142 if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) {
143 DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr);
144 //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1.
145 if (DctSelBase != 0) {
146 //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA.
147 if (DctSelBase < TOMused) {
148 NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused);
150 // Set UMA attribute to interleaved after interleaved region has been swapped
151 LocHeap.BufferHandle = AMD_UMA_INFO_HANDLE;
152 if (HeapLocateBuffer (&LocHeap, &(NBPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
153 UmaInfoPtr = (UMA_INFO *) LocHeap.BufferPtr;
154 UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;