7 * Feature DIMM exclude.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Feat/EXCLUDIMM)
12 * @e \$Revision: 55966 $ @e \$Date: 2011-07-05 10:03:59 -0600 (Tue, 05 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
55 #include "OptionMemory.h"
64 #define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE
66 /*----------------------------------------------------------------------------
67 * DEFINITIONS AND MACROS
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * TYPEDEFS AND STRUCTURES
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * PROTOTYPES OF LOCAL FUNCTIONS
81 *----------------------------------------------------------------------------
85 IN OUT MEM_NB_BLOCK *NBPtr
88 /*----------------------------------------------------------------------------
91 *----------------------------------------------------------------------------
94 /* -----------------------------------------------------------------------------*/
97 * Check and disable Chip selects that fail training for each node.
99 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
101 * @return TRUE - This feature is enabled.
102 * @return FALSE - This feature is not enabled.
106 IN OUT MEM_NB_BLOCK *NBPtr
113 BOOLEAN IsCSIntlvEnabled;
118 ASSERT (NBPtr != NULL);
119 ReserveDCT = NBPtr->Dct;
121 for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
122 NBPtr->SwitchDCT (NBPtr, Dct);
123 if (NBPtr->DCTPtr->Timings.CsTestFail != 0) {
124 // When there is no new failed dimm that needs to be excluded, then no need to go through the process.
125 switch (NBPtr->SharedPtr->DimmExcludeFlag) {
127 // See there is new dimm that needs to be excluded
128 if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) {
129 CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
133 // Do not do any dimm excluding during training
134 // Dimm exclude will be done at the end of training
137 // Exclude all dimms that have failures during training
138 if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) ||
139 ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) {
140 CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
149 if (CsTestFail != 0) {
150 IsCSIntlvEnabled = FALSE;
151 MCTPtr = NBPtr->MCTPtr;
152 MCTPtr->NodeMemSize = 0;
153 NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE;
154 NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0;
155 NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0;
156 NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
157 NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0);
159 if (MCTPtr->GangedMode) {
160 // if ganged mode, disable all pairs of CS that fail.
161 NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail;
164 // if chip select interleaving has been enabled, need to undo it before remapping memory
165 if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) {
166 IsCSIntlvEnabled = TRUE;
170 NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
171 for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
172 NBPtr->SwitchDCT (NBPtr, Dct);
173 if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
174 if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
175 NBPtr->DCTPtr->Timings.DctMemSize = 0;
177 NBPtr->DCTPtr->Timings.CsEnabled = 0;
178 for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
179 NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
182 // Set F2x94[DisDramInterface] = 1 if all chip selects fail training on the DCT
183 if ((NBPtr->DCTPtr->Timings.CsPresent & ~NBPtr->DCTPtr->Timings.CsTestFail) == 0) {
184 NBPtr->DisableDCT (NBPtr);
187 Flag = NBPtr->StitchMemory (NBPtr);
188 ASSERT (Flag == TRUE);
193 NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
195 // Re-enable chip select interleaving when remapping is done.
196 if (IsCSIntlvEnabled) {
197 NBPtr->FeatPtr->InterleaveBanks (NBPtr);
204 NBPtr->SwitchDCT (NBPtr, ReserveDCT);