7 * Feature Channel interleaving support
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Feat/Chintlv)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
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21 * modification, are permitted provided that the following conditions are met:
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23 * notice, this list of conditions and the following disclaimer.
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42 * ***************************************************************************
48 *----------------------------------------------------------------------------
51 *----------------------------------------------------------------------------
61 #include "GeneralServices.h"
66 #define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE
67 /*----------------------------------------------------------------------------
68 * DEFINITIONS AND MACROS
70 *----------------------------------------------------------------------------
72 #define _4GB_ (0x10000 >> 10)
74 /*----------------------------------------------------------------------------
75 * TYPEDEFS AND STRUCTURES
77 *----------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------
81 * PROTOTYPES OF LOCAL FUNCTIONS
83 *----------------------------------------------------------------------------
86 /*----------------------------------------------------------------------------
89 *----------------------------------------------------------------------------
92 /* -----------------------------------------------------------------------------*/
95 * MemFInterleaveChannels:
97 * Applies DIMM channel interleaving if enabled, if not ganged mode, and
98 * there are valid dimms in both channels. Called once per Node.
100 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
102 * @return TRUE - This feature is enabled.
103 * @return FALSE - This feature is not enabled.
107 MemFInterleaveChannels (
108 IN OUT MEM_NB_BLOCK *NBPtr
119 UINT8 DctSelIntLvAddr;
124 MEM_PARAMETER_STRUCT *RefPtr;
127 ASSERT (NBPtr != NULL);
129 RefPtr = NBPtr->RefPtr;
131 DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr;
132 if (RefPtr->EnableChannelIntlv) {
135 if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
136 // HoleBase scaled from [47:16] to [47:26]
137 HoleBase = RefPtr->HoleBase >> 10;
138 HoleSize = _4GB_ - HoleBase;
141 MCTPtr = NBPtr->MCTPtr;
143 HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid);
144 if ((!MCTPtr->GangedMode) &&
145 (MCTPtr->DctData[0].Timings.DctMemSize != 0) &&
146 (MCTPtr->DctData[1].Timings.DctMemSize != 0)) {
147 // DramBase scaled [47:16] to [47:26]
148 DramBase = MCTPtr->NodeSysBase >> 10;
149 // Scale NodeSysLimit [47:16] to [47:26]
150 Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10;
151 Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset);
152 if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) {
153 Dct0Size -= HoleSize;
155 if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) {
156 Dct1Size -= HoleSize;
158 Dct1Size -= Dct0Size;
159 Dct0Size -= DramBase;
161 // Select the bigger size DCT to put in DctSelHi
164 SmallerDct = Dct1Size;
165 if (Dct1Size == Dct0Size) {
168 } else if (Dct1Size > Dct0Size) {
169 SmallerDct = Dct0Size;
173 if (SmallerDct != 0) {
174 DctSelBase = (SmallerDct * 2) + DramBase;
178 if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) {
179 DctSelBase += HoleSize;
181 IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader));
182 NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1);
183 NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn);
184 NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi);
185 NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr);
186 NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1);
188 // DctSelBaseOffset = DctSelBaseAddr - Interleaved region
189 NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct);
191 // Adjust DramHoleOffset
192 if (HoleValid != 0) {
193 HoleOffset = DramBase;
194 if ((DctSelBase < HoleBase) && (DctSelBase != 0)) {
195 HoleOffset += (DctSelBase - DramBase) >> 1;
197 HoleOffset += HoleSize;
198 NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3);
202 // Channel Interleaving is requested but cannot be enabled
204 PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
205 SetMemError (AGESA_WARNING, MCTPtr);