7 * Platform specific settings for DA DDR3 unbuffered dimms
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ardk)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
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21 * modification, are permitted provided that the following conditions are met:
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23 * notice, this list of conditions and the following disclaimer.
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25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
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29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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42 * ***************************************************************************
46 /* This file contains routine that add platform specific support AM3 */
51 #include "PlatformMemoryConfiguration.h"
54 #include "cpuFamRegisters.h"
59 #define FILECODE PROC_MEM_ARDK_DA_MAUDA3_FILECODE
60 /*----------------------------------------------------------------------------
61 * DEFINITIONS AND MACROS
63 *----------------------------------------------------------------------------
66 /*----------------------------------------------------------------------------
67 * TYPEDEFS AND STRUCTURES
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * PROTOTYPES OF LOCAL FUNCTIONS
75 *----------------------------------------------------------------------------
79 *-----------------------------------------------------------------------------
82 *-----------------------------------------------------------------------------
85 STATIC CONST UINT8 ROMDATA DAUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
86 // Even chip select maps to M[B,A]_CKE[0]
87 // Odd chip select maps to M[B,A]_CKE[1]
88 STATIC CONST UINT8 ROMDATA DAUDdr3CKETri[] = {0x55, 0xAA};
89 // Bit 0: M[B,A]0_ODT[0]
90 // Bit 1: M[B,A]1_ODT[0]
91 // Bit 2: M[B,A]0_ODT[1]
92 // Bit 3: M[B,A]1_ODT[1]
93 STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
94 // Bit 0: M[B,A]0_CS_H/L[0]
95 // Bit 1: M[B,A]0_CS_H/L[1]
96 // Bit 2: M[B,A]0_CS_H/L[2]
97 // Bit 3: M[B,A]0_CS_H/L[3]
98 STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
100 /* -----------------------------------------------------------------------------*/
103 * This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
106 * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
107 * @param[in] SocketID Socket number
108 * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
110 * @return AGESA_SUCCESS
111 * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
112 * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
113 * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
114 * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
115 * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
116 * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
117 * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
118 * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
119 * @return CurrentChannel->SlowMode Slow Mode
125 IN OUT MEM_DATA_STRUCT *MemData,
127 IN OUT CH_DEF_STRUCT *CurrentChannel
130 STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
131 {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
132 {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
133 {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
134 {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
136 STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
137 {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
138 {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
139 {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
140 {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
143 STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
144 {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
145 {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
146 {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
147 {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
148 {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
157 UINT16 _DIMMRankType;
164 ASSERT (MemData != 0);
165 ASSERT (CurrentChannel != 0);
174 if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
175 return AGESA_UNSUPPORTED;
177 if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
178 return AGESA_UNSUPPORTED;
180 if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
181 return AGESA_UNSUPPORTED;
184 Loads = CurrentChannel->Loads;
185 Dimms = CurrentChannel->Dimms;
186 Speed = CurrentChannel->DCTPtr->Timings.Speed;
187 DIMMRankType = MemAGetPsRankType (CurrentChannel);
189 if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
190 SlowMode = TRUE; // 2T
191 } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
192 SlowMode = TRUE; // 2T
194 SlowMode = FALSE; // 1T
198 for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
199 if (Speed == PSCfg1Dimm[i].Speed) {
200 if (Loads >= PSCfg1Dimm[i].Loads) {
201 AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
202 DctOdcCtl = PSCfg1Dimm[i].Odc;
204 DctOdcCtl = 0x20113222;
209 ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
211 for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
212 if (Speed == PSCfg2Dimm[i].Speed) {
213 if (Loads <= PSCfg2Dimm[i].Loads) {
214 AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
215 DctOdcCtl = PSCfg2Dimm[i].Odc;
220 ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
224 for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
225 if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
229 _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
230 for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
231 if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
235 if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
236 PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
237 PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
238 PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
239 PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
244 CurrentChannel->MemClkDisMap = (UINT8 *) DAUDdr3CLKDis;
245 CurrentChannel->CKETriMap = (UINT8 *) DAUDdr3CKETri;
246 CurrentChannel->ODTTriMap = (UINT8 *) DAUDdr3ODTTri;
247 CurrentChannel->ChipSelTriMap = (UINT8 *) DAUDdr3CSTri;
249 CurrentChannel->DctEccDqsLike = 0x0403;
250 CurrentChannel->DctEccDqsScale = 0x70;
251 CurrentChannel->DctAddrTmg = AddrTmgCTL;
252 CurrentChannel->DctOdcCtl = DctOdcCtl;
253 for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
254 CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
256 CurrentChannel->SlowMode = SlowMode;
258 return AGESA_SUCCESS;