7 * Contains AMD AGESA Integrated Debug Macros
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 55552 $ @e \$Date: 2011-06-22 09:31:58 -0600 (Wed, 22 Jun 2011) $
14 /*****************************************************************************
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42 ***************************************************************************/
46 #include "OptionsIds.h"
47 #include "cpuRegisters.h"
48 #include "cpuApicUtilities.h"
50 ///Specific time stamp performance analysis which need ids control support
51 #if IDSOPT_CONTROL_ENABLED == TRUE
52 #define PERF_SPEC_TS_ANALYSE(StdHeader)
54 #define PERF_SPEC_TS_ANALYSE(StdHeader)
58 #define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader)
59 #define IDS_GET_MASK32(HighBit, LowBit)
61 #define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap.
62 ///Macro for Ids family feat
63 #define MAKE_IDS_FAMILY_FEAT_ALL_CORES(FEAT_ID, FAMILY, FUNCTION) \
64 {IDS_FEAT_COMMON, IDS_ALL_CORES, FEAT_ID, FAMILY, FUNCTION}
67 // TYPEDEFS, STRUCTURES, ENUMS
70 typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader);
72 ///Structure define for IdsAgesaRunFcnOnApLate
73 typedef struct _IDSAPLATETASK {
74 PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do
75 VOID *ApTaskPara; ///< Point to Ap function parameter1
78 /// Data Structure defining IDS Data in HEAP
79 /// This data structure contains information that is stored in HEAP and will be
80 /// used in IDS backend function. It includes the size of memory to be allocated
81 /// for IDS, the relative offsets of the mapping table IDS setup options, the GRA
82 /// table and the register table to override mem setting. It also includes a base
83 /// address of IDS override image which will be used to control the behavior of
84 /// AGESA testpoint if this feature is enabled.
86 BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset
87 UINT64 IdsImageBase; ///< IDS Override Image Base Address
88 UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap
89 UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table
90 UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table
91 UINT32 IdsExtendOffset; ///< Offset of Ids extend heap
95 /// Data Structure of Parameters for TestPoint_TSC.
97 UINT8 TestPoint; ///< The TestPoint of TestPoint_TSC
98 UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC
101 /// Data Structure of Parameters for TP_Perf_STRUCT.
103 UINT8 Index; ///< The Index of TP_Perf_STRUCT
104 UINT32 TscInMhz; ///< Tsc counter in 1 mhz
105 TestPoint_TSC TP[EndAgesaTps]; ///< The TP of TP_Perf_STRUCT
109 ///Bus speed Optimization
111 IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance
112 IDS_POWER_POLICY_POWER = 1, ///< Power
113 IDS_POWER_POLICY_AUTO = 3, ///< Auto
114 } IDS_NV_AMDBUSSPEEDOPTIMIZATION;
117 #define IDS_ALL_SOCKET 0xFF
118 #define IDS_ALL_MODULE 0xFF
119 #define IDS_ALL_CORE 0xFF
120 #define IDS_ALL_DCT 0xFF
122 #define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFF