5 * External Interface implementation for coherent features.
7 * Contains routines for accessing the interface to the client BIOS,
8 * for support only required for coherent features.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: HyperTransport
13 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
17 *****************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 * ***************************************************************************
49 *----------------------------------------------------------------------------
52 *----------------------------------------------------------------------------
62 #include "htInterface.h"
63 #include "htInterfaceGeneral.h"
64 #include "htInterfaceCoherent.h"
66 #include "heapManager.h"
71 #define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE
72 /*----------------------------------------------------------------------------
73 * DEFINITIONS AND MACROS
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * TYPEDEFS AND STRUCTURES
81 *----------------------------------------------------------------------------
83 /*----------------------------------------------------------------------------
84 * PROTOTYPES OF LOCAL FUNCTIONS
86 *----------------------------------------------------------------------------
88 /*----------------------------------------------------------------------------
91 *----------------------------------------------------------------------------
94 /*----------------------------------------------------------------------------
97 *----------------------------------------------------------------------------
100 /*----------------------------------------------------------------------------------------*/
101 /*----------------------------------------------------------------------------------------*/
103 * Get limits for CPU to CPU Links.
105 * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS}
107 * For each coherent connection this routine is called once. Update the frequency
108 * and width if needed for this Link (usually based on board restriction). This is
109 * used with CPU device capabilities and northbridge limits to compute the default
110 * settings. The input width and frequency are valid, but do not necessarily reflect
111 * the minimum setting that will be chosen.
113 * @param[in] NodeA One Node on which this Link is located
114 * @param[in] LinkA The Link on this Node
115 * @param[in] NodeB The other Node on which this Link is located
116 * @param[in] LinkB The Link on that Node
117 * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
118 * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
119 * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
120 * @param[in] State the input data
124 GetCpu2CpuPcbLimits (
129 IN OUT UINT8 *ABLinkWidthLimit,
130 IN OUT UINT8 *BALinkWidthLimit,
131 IN OUT UINT32 *PcbFreqCap,
135 CPU_TO_CPU_PCB_LIMITS *p;
141 ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
142 ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
144 SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
145 PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
146 SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
147 PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
149 if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) {
150 p = State->HtBlock->CpuToCpuPcbLimitsList;
152 while (p->SocketA != HT_LIST_TERMINAL) {
153 if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
154 ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
155 ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
156 ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
157 ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
158 ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
159 // Found a match, update width and frequency
160 *ABLinkWidthLimit = p->ABLinkWidthLimit;
161 *BALinkWidthLimit = p->BALinkWidthLimit;
162 *PcbFreqCap = p->PcbFreqCap;
171 /*----------------------------------------------------------------------------------------*/
173 * Skip reganging of subLinks.
175 * @HtInterfaceMethod{::F_GET_SKIP_REGANG}
177 * This routine is called whenever two subLinks are both connected to the same CPUs.
178 * Normally, unganged sublinks between the same two CPUs are reganged. Return true
179 * from this routine to leave the Links unganged.
181 * @param[in] NodeA One Node on which this Link is located
182 * @param[in] LinkA The Link on this Node
183 * @param[in] NodeB The other Node on which this Link is located
184 * @param[in] LinkB The Link on that Node
185 * @param[in] State the input data
187 * @retval MATCHED leave Link unganged
188 * @retval POWERED_OFF leave link unganged and power off the paired sublink
189 * @retval UNMATCHED regang Link automatically
201 FINAL_LINK_STATE Result;
207 ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
208 ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
211 SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
212 PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
213 SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
214 PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
216 if (State->HtBlock->SkipRegangList != NULL) {
217 p = State->HtBlock->SkipRegangList;
219 while (p->SocketA != HT_LIST_TERMINAL) {
220 if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
221 ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
222 ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
223 ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
224 ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
225 ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
226 // Found a match return final link state
227 Result = p->LinkState;
237 /*----------------------------------------------------------------------------------------*/
239 * Get a new, empty Hop Count Table, to make one for the installed topology.
241 * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE}
243 * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a
246 * @param[in,out] State Keep our buffer handle.
251 IN OUT STATE_DATA *State
254 ALLOCATE_HEAP_PARAMS AllocHeapParams;
256 AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE);
257 AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE;
258 AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
259 if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
260 State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr;
262 State->HopCountTable = NULL;