5 * Northbridge utility routines.
7 * These routines are needed for support of more than one feature area.
8 * Collect them in this file so build options don't remove them.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: HyperTransport
13 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
17 *****************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 * ***************************************************************************
49 *----------------------------------------------------------------------------
52 *----------------------------------------------------------------------------
63 #include "htNbCommonHardware.h"
64 #include "htNbUtilitiesFam10.h"
69 #define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE
70 /*----------------------------------------------------------------------------
71 * DEFINITIONS AND MACROS
73 *----------------------------------------------------------------------------
76 /*----------------------------------------------------------------------------------------*/
78 * Return the number of cores (1 based count) on Node.
80 * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
82 * @param[in] Node the Node that will be examined
83 * @param[in] Nb this northbridge
85 * @return the number of cores
88 Fam10GetNumCoresOnNode (
99 ASSERT ((Node < MAX_NODES));
101 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
102 MakePciBusFromNode (Node),
103 MakePciDeviceFromNode (Node),
105 REG_NB_CAPABILITY_3XE8);
107 LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
109 // Support Downcoring
112 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
113 MakePciBusFromNode (Node),
114 MakePciDeviceFromNode (Node),
116 REG_NB_DOWNCORE_3X190);
117 LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle);
118 for (i = 0; i < Cores; i++) {
119 if ((Leveling & ((UINT32) 1 << i)) != 0) {
123 return (UINT8) (Result + 1);
126 /*----------------------------------------------------------------------------------------*/
128 * Return the number of cores (1 based count) on Node.
130 * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}.
132 * @param[in] Node the Node that will be examined
133 * @param[in] Nb this northbridge
135 * @return the number of cores
138 Fam10RevDGetNumCoresOnNode (
150 ASSERT ((Node < MAX_NODES));
152 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
153 MakePciBusFromNode (Node),
154 MakePciDeviceFromNode (Node),
156 REG_NB_CAPABILITY_3XE8);
158 LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
159 LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle);
160 Cores = Cores + (Cores2 << 2);
162 // Support Downcoring
165 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
166 MakePciBusFromNode (Node),
167 MakePciDeviceFromNode (Node),
169 REG_NB_DOWNCORE_3X190);
170 LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle);
171 for (i = 0; i < Cores; i++) {
172 if ((Leveling & ((UINT32) 1 << i)) != 0) {
176 return (UINT8) (Result + 1);
179 /*----------------------------------------------------------------------------------------*/
181 * Get the next link for iterating over the links on a node in the correct order.
183 * @HtNbMethod{::F_GET_NEXT_LINK}
185 * Family 10h specific implementation use the Internal Link field in
186 * the northbridge to prioritize internal links in the order.
188 * @param[in] Node The node on which to iterate links.
189 * @param[in,out] Link IN: the current iteration context, OUT: the next link.
190 * @param[in] Nb This Northbridge, access to config pointer.
192 * @retval LinkIteratorExternal The current Link is an external link.
193 * @retval LinkIteratorInternal The current Link is an internal link.
194 * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN).
205 UINT32 InternalLinks;
206 UINT32 ExternalLinks;
208 BOOLEAN IsInternalLink;
209 LINK_ITERATOR_STATUS Status;
211 ASSERT ((Node < MAX_NODES));
212 ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN));
216 // Read IntLnkRoute from the Link Initialization Status register.
217 // (Note that this register field is not reserved prior to rev D, but should be zero.)
218 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
219 MakePciBusFromNode (Node),
220 MakePciDeviceFromNode (Node),
222 REG_HT_LINK_INITIALIZATION_0X1A0);
224 LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle);
225 // The external links are all possible links which are not Internal
226 ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks);
227 // Can't have no possible links!
228 ASSERT ((ExternalLinks != 0) || (InternalLinks != 0));
231 if (*Link == LINK_ITERATOR_BEGIN) {
232 // If the request is for the first link (BEGIN), get it
233 if (InternalLinks != 0) {
234 *Link = LibAmdBitScanForward (InternalLinks);
235 Status = LinkIteratorInternal;
237 *Link = LibAmdBitScanForward (ExternalLinks);
238 Status = LinkIteratorExternal;
241 // If the iterator is not at the beginning, search for the next Link starting from the
243 HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1);
244 IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0);
245 if (IsInternalLink && (HigherLinks != 0)) {
246 // We are still on internal links and there are more to do.
247 *Link = LibAmdBitScanForward (HigherLinks);
248 Status = LinkIteratorInternal;
250 if (IsInternalLink) {
251 // We are transitioning now from internal to external, so get the first external link
252 HigherLinks = ExternalLinks;
254 // We are already iterating over external links, so get the next one
255 HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1);
257 if (HigherLinks != 0) {
258 *Link = LibAmdBitScanForward (HigherLinks);
259 Status = LinkIteratorExternal;
261 // The end of all links
262 *Link = LINK_ITERATOR_BEGIN;
263 Status = LinkIteratorEnd;
270 /*----------------------------------------------------------------------------------------*/
272 * Get Info about Module Type of this northbridge
274 * @HtNbMethod{::F_GET_MODULE_INFO}
276 * Provide the Processor module type, single or multi, and the node's module id.
278 * @param[in] Node the Node
279 * @param[out] ModuleType 0 for Single, 1 for Multi
280 * @param[out] Module The module number of this node (0 if Single)
281 * @param[in] Nb this northbridge
287 OUT UINT8 *ModuleType,
296 ASSERT (Node < MAX_NODES);
298 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
299 MakePciBusFromNode (Node),
300 MakePciDeviceFromNode (Node),
302 REG_NB_CAPABILITY_3XE8);
303 LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle);
304 LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle);
306 *ModuleType = (UINT8) MultNodeCpu;
307 *Module = (UINT8) IntNodeNum;
310 /*----------------------------------------------------------------------------------------*/
312 * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
314 * @HtNbMethod{::F_GET_SOCKET}
316 * The hardware socket naming method is not available for Family 10h prior to rev D.
318 * @param[in] Node The node for which we want the socket id.
319 * @param[in] TempNode The temporary node id route where the node can be accessed.
320 * @param[in] Nb Our Northbridge.
322 * @return The Socket Id
331 ASSERT ((Node < MAX_NODES));
332 ASSERT (TempNode < MAX_NODES);
337 /*----------------------------------------------------------------------------------------*/
339 * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
341 * @HtNbMethod{::F_GET_SOCKET}
343 * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr.
345 * @param[in] Node The node for which we want the socket id.
346 * @param[in] TempNode The temporary node id route where the node can be accessed.
347 * @param[in] Nb Our Northbridge.
349 * @return The Socket Id
361 ASSERT ((TempNode < MAX_NODES));
362 ASSERT ((Node < MAX_NODES));
364 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode),
365 MakePciBusFromNode (TempNode),
366 MakePciDeviceFromNode (TempNode),
368 REG_NB_SBI_CONTROL_3X1E4);
369 LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle);
370 return ((UINT8) Socket);
373 /*----------------------------------------------------------------------------------------*/
375 * Post info to AP cores via a mailbox.
377 * @HtNbMethod{::F_POST_MAILBOX}
379 * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
382 * @param[in] Node the Node
383 * @param[in] ApMailboxes The info to post
384 * @param[in] Nb this northbridge
390 IN AP_MAILBOXES ApMailboxes,
396 ASSERT (Node < MAX_NODES);
398 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
399 MakePciBusFromNode (Node),
400 MakePciDeviceFromNode (Node),
402 REG_NB_MCA_LINK_THRESHOLD_3X168);
403 LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle);
404 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
405 MakePciBusFromNode (Node),
406 MakePciDeviceFromNode (Node),
408 REG_NB_MCA_L3_THRESHOLD_3X170);
409 LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
412 /*----------------------------------------------------------------------------------------*/
414 * Retrieve info from a node's mailbox.
416 * @HtNbMethod{::F_RETRIEVE_MAILBOX}
418 * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
421 * @param[in] Node the Node
422 * @param[in] Nb this northbridge
424 * @return The ap mailbox info
428 Fam10RetrieveMailbox (
434 AP_MAIL_INFO ApMailInfo;
436 ASSERT (Node < MAX_NODES);
438 Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
439 MakePciBusFromNode (Node),
440 MakePciDeviceFromNode (Node),
442 REG_NB_MCA_LINK_THRESHOLD_3X168);
443 LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle);