5 * AMD AGESA Basic Level Public APIs
7 * Contains basic Level Initialization routines.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: Interface
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
58 #include "cpuRegisters.h"
59 #include "cpuApicUtilities.h"
60 #include "cpuPostInit.h"
61 #include "CommonInits.h"
62 #include "cpuFeatures.h"
63 #include "heapManager.h"
64 #include "CreateStruct.h"
68 #define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE
69 /*----------------------------------------------------------------------------------------
70 * D E F I N I T I O N S A N D M A C R O S
71 *----------------------------------------------------------------------------------------
75 /*----------------------------------------------------------------------------------------
76 * T Y P E D E F S A N D S T R U C T U R E S
77 *----------------------------------------------------------------------------------------
81 /*----------------------------------------------------------------------------------------
82 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
83 *----------------------------------------------------------------------------------------
87 /*----------------------------------------------------------------------------------------
88 * E X P O R T E D F U N C T I O N S
89 *----------------------------------------------------------------------------------------
92 /*---------------------------------------------------------------------------------------*/
94 * Main entry point for the AMD_INIT_RESUME function.
96 * This entry point is responsible for performing silicon device and memory
97 * re-initialization for the resume boot path.
99 * @param[in] ResumeParams Required input parameters for the AMD_INIT_RESUME
102 * @return Aggregated status across all internal AMD resume calls invoked.
107 IN AMD_RESUME_PARAMS *ResumeParams
111 AGESA_STATUS ReturnStatus;
112 AGESA_STATUS AmdInitResumeStatus;
113 BSC_AP_MSR_SYNC ApMsrSync[4];
115 AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader);
116 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume Start\n");
118 AmdInitResumeStatus = AGESA_SUCCESS;
120 ASSERT (ResumeParams != NULL);
122 if (ResumeParams->S3DataBlock.NvStorage != NULL) {
124 MemS3ResumeInitNB (&ResumeParams->StdHeader);
126 // Restore registers before exiting self refresh
127 RestorePreESRContext (&OrMaskPtr,
128 ResumeParams->S3DataBlock.NvStorage,
130 &ResumeParams->StdHeader);
132 ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader);
133 if (ReturnStatus > AmdInitResumeStatus) {
134 AmdInitResumeStatus = ReturnStatus;
136 if (ReturnStatus == AGESA_SUCCESS) {
138 // Restore registers after exiting self refresh
139 RestorePostESRContext (OrMaskPtr,
140 ResumeParams->S3DataBlock.NvStorage,
142 &ResumeParams->StdHeader);
144 ApMsrSync[0].RegisterAddress = SYS_CFG;
145 ApMsrSync[1].RegisterAddress = TOP_MEM;
146 ApMsrSync[2].RegisterAddress = TOP_MEM2;
147 ApMsrSync[3].RegisterAddress = 0;
148 SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader);
150 IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after S3 AP MTRR sync\n");
151 ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
152 if (ReturnStatus > AmdInitResumeStatus) {
153 AmdInitResumeStatus = ReturnStatus;
158 // Set TscFreqSel at the rate specified by the core P0
159 SetCoresTscFreqSel (&ResumeParams->StdHeader);
161 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume End\n");
162 // HDT out of All Aps
163 IDS_HDT_CONSOLE_FLUSH_BUFFER (&ResumeParams->StdHeader);
164 // Relinquish control of all APs to IBV
165 RelinquishControlOfAllAPs (&ResumeParams->StdHeader);
168 IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &ResumeParams->StdHeader);
169 IDS_OPTION_HOOK (IDS_AFTER_S3_RESUME, NULL, &ResumeParams->StdHeader);
170 AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader);
171 return (AmdInitResumeStatus);
174 /*---------------------------------------------------------------------------------------*/
176 * Constructor for the AMD_INIT_RESUME function.
178 * This routine is responsible for setting default values for the
179 * input parameters needed by the AMD_INIT_RESUME entry point.
181 * @param[in] StdHeader The standard header.
182 * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME
185 * @retval AGESA_SUCCESS Always Succeeds.
189 AmdInitResumeInitializer (
190 IN AMD_CONFIG_PARAMS *StdHeader,
191 IN OUT AMD_RESUME_PARAMS *ResumeParams
194 ASSERT (StdHeader != NULL);
195 ASSERT (ResumeParams != NULL);
197 ResumeParams->StdHeader = *StdHeader;
199 AmdS3ParamsInitializer (&ResumeParams->S3DataBlock);
200 CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
202 return AGESA_SUCCESS;
205 /*---------------------------------------------------------------------------------------*/
207 * Destructor for the AMD_INIT_RESUME function.
209 * This routine is responsible for deallocation of heap space allocated during
210 * AMD_INIT_RESUME entry point.
212 * @param[in] StdHeader The standard header.
213 * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME
216 * @retval AGESA_STATUS
220 AmdInitResumeDestructor (
221 IN AMD_CONFIG_PARAMS *StdHeader,
222 IN OUT AMD_RESUME_PARAMS *ResumeParams
225 AGESA_STATUS ReturnStatus;
228 ASSERT (ResumeParams != NULL);
230 ReturnStatus = AGESA_SUCCESS;
232 // Deallocate heap space allocated during memory S3 resume
233 RetVal = MemS3Deallocate (&ResumeParams->StdHeader);
234 if (RetVal > ReturnStatus) {
235 ReturnStatus = RetVal;