5 * AMD CPU Power Management Single Socket Functions.
7 * Contains code for doing power management for single socket CPU
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $
16 ******************************************************************************
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43 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
53 #include "GeneralServices.h"
54 #include "cpuRegisters.h"
55 #include "cpuApicUtilities.h"
56 #include "cpuFamilyTranslation.h"
57 #include "cpuPowerMgmtSystemTables.h"
58 #include "cpuPowerMgmtSingleSocket.h"
63 #define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE
64 /*----------------------------------------------------------------------------------------
65 * D E F I N I T I O N S A N D M A C R O S
66 *----------------------------------------------------------------------------------------
69 /*----------------------------------------------------------------------------------------
70 * T Y P E D E F S A N D S T R U C T U R E S
71 *----------------------------------------------------------------------------------------
74 /*----------------------------------------------------------------------------------------
75 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
76 *----------------------------------------------------------------------------------------
79 /*----------------------------------------------------------------------------------------
80 * E X P O R T E D F U N C T I O N S
81 *----------------------------------------------------------------------------------------
84 /*---------------------------------------------------------------------------------------*/
86 * Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
88 * This function will simply invoke the task on the executing core. This must be
89 * run by the system BSC only.
91 * @param[in] TaskPtr Function descriptor
92 * @param[in] StdHeader Config handle for library and services
93 * @param[in] ConfigParams AMD entry point's CPU parameter structure
97 RunCodeOnAllSystemCore0sSingle (
99 IN AMD_CONFIG_PARAMS *StdHeader,
100 IN VOID *ConfigParams
103 ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
107 /*---------------------------------------------------------------------------------------*/
109 * Single socket BSC call to determine the maximum number of steps that any single
110 * processor needs to execute.
112 * This function simply returns the number of steps that the BSC needs.
114 * @param[out] NumSystemSteps Maximum number of system steps required
115 * @param[in] StdHeader Config handle for library and services
119 GetNumberOfSystemPmStepsPtrSingle (
120 OUT UINT8 *NumSystemSteps,
121 IN AMD_CONFIG_PARAMS *StdHeader
124 SYS_PM_TBL_STEP *Ignored;
125 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
127 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
128 FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, NumSystemSteps, StdHeader);
132 /*---------------------------------------------------------------------------------------*/
134 * Single socket call to determine the frequency that the northbridges must run.
136 * This function simply returns the executing core's NB frequency, and that all
137 * NB frequencies are equivalent.
139 * @param[in] NbPstate NB P-state number to check (0 = fastest)
140 * @param[in] PlatformConfig Platform profile/build option config structure.
141 * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
142 * @param[out] SystemNbCofDenominator NB frequency denominator for the system
143 * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
144 * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
145 * @param[in] StdHeader Config handle for library and services
147 * @retval TRUE At least one processor has NbPstate enabled.
148 * @retval FALSE NbPstate is disabled on all CPUs
152 GetSystemNbCofSingle (
154 IN PLATFORM_CONFIGURATION *PlatformConfig,
155 OUT UINT32 *SystemNbCofNumerator,
156 OUT UINT32 *SystemNbCofDenominator,
157 OUT BOOLEAN *SystemNbCofsMatch,
158 OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
159 IN AMD_CONFIG_PARAMS *StdHeader
164 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
166 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
167 *SystemNbCofsMatch = TRUE;
168 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
169 *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
173 SystemNbCofNumerator,
174 SystemNbCofDenominator,
177 return *NbPstateIsEnabledOnAllCPUs;
181 /*---------------------------------------------------------------------------------------*/
183 * Single socket call to determine if the BIOS is responsible for updating the
184 * northbridge operating frequency and voltage.
186 * This function simply returns whether or not the executing core needs NB COF
189 * @param[in] StdHeader Config handle for library and services
191 * @retval TRUE BIOS needs to set up NB frequency and voltage
192 * @retval FALSE BIOS does not need to set up NB frequency and voltage
196 GetSystemNbCofVidUpdateSingle (
197 IN AMD_CONFIG_PARAMS *StdHeader
202 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
204 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
205 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
206 return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
210 /*---------------------------------------------------------------------------------------*/
212 * Single socket call to determine the most severe AGESA_STATUS return value after
213 * processing the power management initialization tables.
215 * This function searches the event log for the most severe error and returns
216 * the status code. This function must be called by the BSC only.
218 * @param[in] StdHeader Config handle for library and services
220 * @return The most severe error code from power management init
224 GetEarlyPmErrorsSingle (
225 IN AMD_CONFIG_PARAMS *StdHeader
229 AGESA_EVENT EventLogEntry;
230 AGESA_STATUS ReturnCode;
232 ASSERT (IsBsp (StdHeader, &ReturnCode));
234 ReturnCode = AGESA_SUCCESS;
235 for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
236 if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
237 if (EventLogEntry.EventClass > ReturnCode) {
238 ReturnCode = EventLogEntry.EventClass;
247 * Single socket call to loop through all Nb Pstates, comparing the NB frequencies
248 * to determine the slowest in the system. This routine also returns the NB P0 frequency.
250 * @param[in] PlatformConfig Platform profile/build option config structure.
251 * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
252 * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
253 * @param[in] StdHeader Config handle for library and services
257 IN PLATFORM_CONFIGURATION *PlatformConfig,
258 OUT UINT32 *MinSysNbFreq,
259 OUT UINT32 *MinP0NbFreq,
260 IN AMD_CONFIG_PARAMS *StdHeader
264 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
266 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
267 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
268 FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices,
276 /*---------------------------------------------------------------------------------------*/
278 * Get PCI Config Space Address for the current running core.
280 * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
281 * @param[in] StdHeader Header for library and services.
283 * @retval TRUE The core is present, PCI Address valid
284 * @retval FALSE The core is not present, PCI Address not valid.
287 GetCurrPciAddrSingle (
288 OUT PCI_ADDR *PciAddress,
289 IN AMD_CONFIG_PARAMS *StdHeader
292 PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
297 /*---------------------------------------------------------------------------------------*/
299 * Writes to all nodes on the executing core's socket.
301 * @param[in] PciAddress The Function and Register to update
302 * @param[in] Mask The bitwise AND mask to apply to the current register value
303 * @param[in] Data The bitwise OR mask to apply to the current register value
304 * @param[in] StdHeader Header for library and services.
308 ModifyCurrSocketPciSingle (
309 IN PCI_ADDR *PciAddress,
312 IN AMD_CONFIG_PARAMS *StdHeader
315 UINT32 LocalPciRegister;
318 Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
319 Reg.Address.Function = PciAddress->Address.Function;
320 Reg.Address.Register = PciAddress->Address.Register;
321 LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
322 LocalPciRegister &= Mask;
323 LocalPciRegister |= Data;
324 LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);