5 * AMD CPU Execution Cache Allocation functions.
7 * Contains code for doing Execution Cache Allocation for ROM space
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 50472 $ @e \$Date: 2011-04-11 01:57:56 -0600 (Mon, 11 Apr 2011) $
16 ******************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
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22 * modification, are permitted provided that the following conditions are met:
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43 ******************************************************************************
46 #ifndef _CPU_CACHE_INIT_H_
47 #define _CPU_CACHE_INIT_H_
49 /*----------------------------------------------------------------------------
50 * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
52 *----------------------------------------------------------------------------
55 /*-----------------------------------------------------------------------------
56 * DEFINITIONS AND MACROS
58 *-----------------------------------------------------------------------------
60 #define BSP_STACK_SIZE_64K 65536
61 #define BSP_STACK_SIZE_32K 32768
63 #define CORE0_STACK_SIZE 16384
64 #define CORE1_STACK_SIZE 4096
66 #define AMD_MTRR_FIX4K_BASE 0x268
67 #define AMD_MTRR_VARIABLE_BASE6 0x20C
68 #define AMD_MTRR_VARIABLE_BASE7 0x20E
70 #define WP_IO 0x0505050505050505
72 #define AGESA_CACHE_SIZE_REDUCED 1
73 #define AGESA_CACHE_REGIONS_ACROSS_1MB 2
74 #define AGESA_CACHE_REGIONS_ACROSS_4GB 3
75 #define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
76 #define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
77 #define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
78 #define AGESA_DEALLOCATE_CACHE_REGIONS 7
80 /*----------------------------------------------------------------------------
81 * TYPEDEFS, STRUCTURES, ENUMS
83 *----------------------------------------------------------------------------
85 /// Cache-As-Ram Executable region allocation modes
87 LimitedByL2Size, ///< Execution space must be allocated from L2
88 InfiniteExe, ///< Family can support unlimited Execution space
89 MaxCarExeMode ///< Used as limit or bounds check
94 IN UINT32 BspStackSize; ///< Stack size of BSP
95 IN UINT32 Core0StackSize; ///< Stack size of primary cores
96 IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
97 IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
98 IN UINT32 SharedMemSize; ///< Shared memory size
99 IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
100 IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
101 IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
102 IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
105 /// Merged memory region overlap type
107 EmptySet, ///< One of the regions is zero length
108 Disjoint, ///< The two regions do not touch
109 Adjacent, ///< one region is next to the other, no gap
110 CommonEnd, ///< regions overlap with a common end point
111 Extending, ///< the 2nd region is extending the size of the 1st
112 Contained, ///< the 2nd region is wholely contained inside the 1st
113 CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
114 Identity, ///< the two regions are the same
115 CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
116 NotCombinable ///< the combined regions do not follow the cache block rules
119 /// Result of merging two memory regions for cache coverage
121 IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
122 IN OUT UINT32 MergedSize; ///< Size of the merged regions
123 OUT UINT32 OverlapAmount; ///< the size of the overlapping section
124 OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
125 } MERGED_CACHE_REGION;
127 /*----------------------------------------------------------------------------
128 * FUNCTIONS PROTOTYPE
130 *----------------------------------------------------------------------------
133 AllocateExecutionCache (
134 IN AMD_CONFIG_PARAMS *StdHeader,
135 IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
138 #endif // _CPU_CACHE_INIT_H_