5 * AMD AGESA CPU C6 feature support code.
7 * Contains code that declares the AGESA CPU C6 related APIs
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: CPU/Feature
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
16 ******************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
53 #include "cpuRegisters.h"
54 #include "cpuEarlyInit.h"
55 #include "GeneralServices.h"
56 #include "cpuFamilyTranslation.h"
57 #include "OptionMultiSocket.h"
58 #include "cpuApicUtilities.h"
59 #include "cpuServices.h"
60 #include "cpuFeatures.h"
61 #include "cpuC6State.h"
66 #define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE
68 /*----------------------------------------------------------------------------------------
69 * D E F I N I T I O N S A N D M A C R O S
70 *----------------------------------------------------------------------------------------
73 /*----------------------------------------------------------------------------------------
74 * T Y P E D E F S A N D S T R U C T U R E S
75 *----------------------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------------------
79 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
80 *----------------------------------------------------------------------------------------
86 IN AMD_CONFIG_PARAMS *StdHeader,
87 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
90 /*----------------------------------------------------------------------------------------
91 * E X P O R T E D F U N C T I O N S
92 *----------------------------------------------------------------------------------------
94 extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
95 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
97 /*---------------------------------------------------------------------------------------*/
99 * Should C6 be enabled
101 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
102 * @param[in] StdHeader Config Handle for library, services.
104 * @retval TRUE C6 is supported.
105 * @retval FALSE C6 cannot be enabled.
111 IN PLATFORM_CONFIGURATION *PlatformConfig,
112 IN AMD_CONFIG_PARAMS *StdHeader
117 C6_FAMILY_SERVICES *FamilyServices;
120 if (PlatformConfig->CStateMode == CStateModeC6) {
122 for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
123 if (IsProcessorPresent (Socket, StdHeader)) {
124 GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
125 if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) {
135 /*---------------------------------------------------------------------------------------*/
137 * Enable the C6 C-state
139 * @param[in] EntryPoint Timepoint designator.
140 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
141 * @param[in] StdHeader Config Handle for library, services.
143 * @retval AGESA_SUCCESS Always succeeds.
148 InitializeC6Feature (
149 IN UINT64 EntryPoint,
150 IN PLATFORM_CONFIGURATION *PlatformConfig,
151 IN AMD_CONFIG_PARAMS *StdHeader
159 UINT32 NumberOfSockets;
160 UINT32 NumberOfCores;
162 AMD_CPU_EARLY_PARAMS CpuEarlyParams;
163 C6_FAMILY_SERVICES *C6FamilyServices;
164 AGESA_STATUS IgnoredSts;
166 CpuEarlyParams.PlatformConfig = *PlatformConfig;
168 TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
169 TaskPtr.DataTransfer.DataSizeInDwords = 2;
170 TaskPtr.DataTransfer.DataPtr = &EntryPoint;
171 TaskPtr.DataTransfer.DataTransferFlags = 0;
172 TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
173 OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
175 if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
176 // Load any required microcode patches on both normal boot and resume from S3.
177 IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
178 GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader);
179 if (C6FamilyServices != NULL) {
180 C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
183 // run code on all APs
184 TaskPtr.DataTransfer.DataSizeInDwords = 0;
185 TaskPtr.ExeFlags = 0;
187 NumberOfSockets = GetPlatformNumberOfSockets ();
189 for (Socket = 0; Socket < NumberOfSockets; Socket++) {
190 if (IsProcessorPresent (Socket, StdHeader)) {
191 GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader);
192 if (C6FamilyServices != NULL) {
193 // run code on all APs
194 TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
195 if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
196 for (Core = 0; Core < NumberOfCores; Core++) {
197 if ((Socket != BscSocket) || (Core != BscCoreNum)) {
198 ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
206 return AGESA_SUCCESS;
210 /*---------------------------------------------------------------------------------------*/
212 * 'Local' core 0 task to enable C6 on it's socket.
214 * @param[in] EntryPoint Timepoint designator.
215 * @param[in] StdHeader Config Handle for library, services.
216 * @param[in] CpuEarlyParams Service parameters.
223 IN AMD_CONFIG_PARAMS *StdHeader,
224 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
228 C6_FAMILY_SERVICES *FamilyServices;
230 IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n");
232 GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
233 FamilyServices->InitializeC6 (FamilyServices,
234 *((UINT64 *) EntryPoint),
235 &CpuEarlyParams->PlatformConfig,
239 /*---------------------------------------------------------------------------------------*/
241 * Reload microcode patch after memory is initialized.
243 * @param[in] StdHeader Config Handle for library, services.
247 ReloadMicrocodePatchAfterMemInit (
248 IN AMD_CONFIG_PARAMS *StdHeader
251 LoadMicrocodePatch (StdHeader);
255 CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State =
258 (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),