5 * AMD Family_15 P-State power check
7 * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
8 * described in the BKDG.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: CPU/Family/0x15
13 * @e \$Revision: 56273 $ @e \$Date: 2011-07-11 12:53:52 -0600 (Mon, 11 Jul 2011) $
17 ******************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
40 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ******************************************************************************
47 /*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
53 #include "cpuF15PowerMgmt.h"
54 #include "cpuRegisters.h"
55 #include "cpuApicUtilities.h"
56 #include "cpuFamilyTranslation.h"
57 #include "cpuF15PowerCheck.h"
58 #include "cpuServices.h"
59 #include "GeneralServices.h"
60 #include "OptionMultiSocket.h"
65 #define FILECODE PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE
67 /*----------------------------------------------------------------------------------------
68 * D E F I N I T I O N S A N D M A C R O S
69 *----------------------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------------------
73 * T Y P E D E F S A N D S T R U C T U R E S
74 *----------------------------------------------------------------------------------------
77 /*----------------------------------------------------------------------------------------
78 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
79 *----------------------------------------------------------------------------------------
83 F15PwrCheckAllCoresGoToLegalPstate (
85 IN AMD_CONFIG_PARAMS *StdHeader
90 F15PwrCheckPrimaryCoresAdjustPstates (
92 IN AMD_CONFIG_PARAMS *StdHeader
97 F15PwrCheckAllCoresGoToCurrentPs (
99 IN AMD_CONFIG_PARAMS *StdHeader
104 F15PmPwrChkCopyPstate (
107 IN AMD_CONFIG_PARAMS *StdHeader
110 /*----------------------------------------------------------------------------------------
111 * E X P O R T E D F U N C T I O N S
112 *----------------------------------------------------------------------------------------
114 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
115 /*---------------------------------------------------------------------------------------*/
117 * Family 15h core 0 entry point for performing the family 15h Processor-
118 * Systemboard Power Delivery Check.
120 * The steps are as follows:
121 * 1. Starting with SW P0, loop through all P-states until a passing state
122 * is found. A passing state is one in which the current required by
123 * the CPU is less than the maximum amount of current that the system
124 * can provide to the CPU. If P0 is under the limit, no further action
126 * 2. If at least one P-State is under the limit & at least one P-State is
127 * over the limit, the BIOS must:
128 * a. If the processor's current P-State is disabled by the power check,
129 * then the BIOS must request a transition to an enabled P-state
130 * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
131 * to reflect the new value.
132 * b. Program D18F4x15C[BoostSrc] to zero.
133 * c. Copy the contents of the enabled P-state MSRs to the highest
134 * performance P-state locations.
135 * d. Request a P-state transition to the P-state MSR containing the
136 * COF/VID values currently applied.
137 * e. Adjust the following P-state parameters affected by the P-state
138 * MSR copy by subtracting the number of P-states that are disabled
139 * by the power check.
140 * 1. F3x64[HtcPstateLimit]
141 * 2. F3x68[SwPstateLimit]
142 * 3. F3xDC[PstateMaxVal]
143 * 3. If all P-States are over the limit, the BIOS must:
144 * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
145 * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
146 * MSRC001_0063[CurPstate] to reflect the new value.
147 * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state
148 * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR.
149 * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
150 * [CurPstate] to reflect the new value.
151 * c. Adjust the following P-state parameters to zero:
152 * 1. F3x64[HtcPstateLimit]
153 * 2. F3x68[SwPstateLimit]
154 * 3. F3xDC[PstateMaxVal]
155 * d. Program D18F4x15C[BoostSrc] to zero.
157 * @param[in] FamilySpecificServices The current Family Specific Services.
158 * @param[in] CpuEarlyParams Service parameters
159 * @param[in] StdHeader Config handle for library and services.
164 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
165 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
166 IN AMD_CONFIG_PARAMS *StdHeader
173 UINT32 LocalPciRegister;
183 UINT64 LocalMsrRegister;
184 BOOLEAN AllPstatesDisabled;
187 AGESA_STATUS IgnoredSts;
188 PWRCHK_ERROR_DATA ErrorData;
190 // get the socket number
191 IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
195 // get the Max P-state value
196 for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
197 LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
198 if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
203 ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
204 GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
205 PciAddress.Address.Function = FUNC_4;
206 PciAddress.Address.Register = CPB_CTRL_REG;
207 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
208 ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
210 // Starting with SW P0, loop through all P-states until a passing state
211 // is found. A passing state is one in which the current required by
212 // the CPU is less than the maximum amount of current that the system
213 // can provide to the CPU. If P0 is under the limit, no further action
216 AllPstatesDisabled = TRUE;
218 for (Pstate = ErrorData.NumberOfBoostStates; Pstate < ErrorData.HwPstateNumber; Pstate++) {
219 if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
220 if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
221 // Add to event log the Pstate that exceeded the current limit
222 PutEventLog (AGESA_WARNING,
223 CPU_EVENT_PM_PSTATE_OVERCURRENT,
224 Socket, Pstate, 0, 0, StdHeader);
227 AllPstatesDisabled = FALSE;
234 ErrorData.NumberOfSwPstatesDisabled = DisPsNum;
236 if (AllPstatesDisabled) {
237 // All P-states are over the limit
238 PutEventLog (AGESA_FATAL,
239 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
240 Socket, 0, 0, 0, StdHeader);
241 ErrorData.NumberOfSwPstatesDisabled--;
244 // Launch APs to transition to a valid P-state
245 TaskPtr.FuncAddress.PfApTaskI = F15PwrCheckAllCoresGoToLegalPstate;
246 TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
247 TaskPtr.DataTransfer.DataPtr = &ErrorData;
248 TaskPtr.DataTransfer.DataTransferFlags = 0;
249 TaskPtr.ExeFlags = WAIT_FOR_CORE;
250 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
252 // If any software P-states are disabled, then program D18F4x15C[BoostSrc] to zero.
253 AndMask = 0xFFFFFFFF;
254 ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0;
256 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C
258 // Modify P-state MSRs on one core per die
259 TaskPtr.FuncAddress.PfApTaskI = F15PwrCheckPrimaryCoresAdjustPstates;
261 for (ModuleIndex = 0; ModuleIndex < GetPlatformNumberOfModules (); ModuleIndex++) {
262 if (ModuleIndex != Module) {
263 if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) {
264 ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader);
268 F15PwrCheckPrimaryCoresAdjustPstates (&ErrorData, StdHeader);
270 // Launch APs to transition to the current P-state at its new location
271 TaskPtr.FuncAddress.PfApTaskI = F15PwrCheckAllCoresGoToCurrentPs;
272 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
275 // F3x64[HtPstatelimit] -= disPsNum
276 // F3x68[SwPstateLimit] -= disPsNum
277 // F3xDC[PstateMaxVal] -= disPsNum
279 PciAddress.Address.Function = FUNC_3;
280 PciAddress.Address.Register = HTC_REG;
281 AndMask = 0xFFFFFFFF;
282 ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
284 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
285 PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
286 if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
287 PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
288 ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
290 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
292 PciAddress.Address.Register = SW_PS_LIMIT_REG;
293 AndMask = 0xFFFFFFFF;
294 ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0;
296 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
297 PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit;
298 if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
299 PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
300 ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit;
302 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
304 PciAddress.Address.Register = CPTC2_REG;
305 AndMask = 0xFFFFFFFF;
306 ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
308 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
309 PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
310 if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
311 PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
312 ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
314 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
318 /*---------------------------------------------------------------------------------------*/
320 * First phase core-level error handler called if any p-states were determined
321 * to be out of range for the mother board.
323 * Transitions to a legal P-state if necessary (steps 2a and 3a) on each core.
325 * @param[in] ErrorData Details about the error condition.
326 * @param[in] StdHeader Config handle for library and services.
331 F15PwrCheckAllCoresGoToLegalPstate (
333 IN AMD_CONFIG_PARAMS *StdHeader
337 UINT64 LocalMsrRegister;
338 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
340 if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
341 LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
342 CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
344 if (CurrentPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) {
345 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
346 FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader);
351 /*---------------------------------------------------------------------------------------*/
353 * Core-level error handler called if any p-states were determined to be out
354 * of range for the mother board.
356 * This function implements steps 2c and the first half of 3b on one core per die.
358 * @param[in] ErrorData Details about the error condition.
359 * @param[in] StdHeader Config handle for library and services.
364 F15PwrCheckPrimaryCoresAdjustPstates (
366 IN AMD_CONFIG_PARAMS *StdHeader
371 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
373 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
375 HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
376 for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) {
377 F15PmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader);
380 // Disable the appropriate P-states if any, starting from HW Pmin
381 for (i = 0; i < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; i++) {
382 FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader);
386 /*---------------------------------------------------------------------------------------*/
388 * Second phase core-level error handler called if any p-states were determined
389 * to be out of range for the mother board.
391 * Transitions to the core's current P-state in its new location (steps 2d and
392 * the second half of 3b) on each core.
394 * @param[in] ErrorData Details about the error condition.
395 * @param[in] StdHeader Config handle for library and services.
400 F15PwrCheckAllCoresGoToCurrentPs (
402 IN AMD_CONFIG_PARAMS *StdHeader
406 UINT64 LocalMsrRegister;
407 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
409 if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
410 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
412 LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
413 CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate) - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
415 FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
419 /*---------------------------------------------------------------------------------------*/
421 * Copies the contents of one P-State MSR to another.
423 * @param[in] Dest Destination p-state number
424 * @param[in] Src Source p-state number
425 * @param[in] StdHeader Config handle for library and services
430 F15PmPwrChkCopyPstate (
433 IN AMD_CONFIG_PARAMS *StdHeader
436 UINT64 LocalMsrRegister;
438 LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
439 LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);