src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD CPU Cache Flush On Halt Function for Family 15h Orochi.
   6  *
   7  * Contains code to initialize Cache Flush On Halt feature for Family 15h Orochi.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  CPU/Family/0x15/OR
  12  * @e \$Revision: 55600 $   @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
  13  *
  14  */
  15 /*
  16  ******************************************************************************
  17  *
  18  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  ******************************************************************************
  44  *----------------------------------------------------------------------------
  45  */
  46
  47
  48 /*
  49  *----------------------------------------------------------------------------
  50  *                                MODULES USED
  51  *
  52  *----------------------------------------------------------------------------
  53  */
  54 #include "AGESA.h"
  55 #include "amdlib.h"
  56 #include "cpuRegisters.h"
  57 #include "cpuServices.h"
  58 #include "cpuFamilyTranslation.h"
  59 #include "cpuPostInit.h"
  60 #include "cpuF15PowerMgmt.h"
  61 #include "cpuF15OrPowerMgmt.h"
  62 #include "cpuFeatures.h"
  63 #include "F15PackageType.h"
  64 #include "OptionMultiSocket.h"
  65 #include "Filecode.h"
  66 CODE_GROUP (G3_DXE)
  67 RDATA_GROUP (G3_DXE)
  68
  69 #define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE
  70
  71 /*----------------------------------------------------------------------------
  72  *                          DEFINITIONS AND MACROS
  73  *
  74  *----------------------------------------------------------------------------
  75  */
  76 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
  77
  78 /*----------------------------------------------------------------------------
  79  *                           TYPEDEFS AND STRUCTURES
  80  *
  81  *----------------------------------------------------------------------------
  82  */
  83
  84 /*----------------------------------------------------------------------------------------
  85  *                          E X P O R T E D    F U N C T I O N S
  86  *----------------------------------------------------------------------------------------
  87  */
  88
  89 /*----------------------------------------------------------------------------
  90  *                        PROTOTYPES OF LOCAL FUNCTIONS
  91  *
  92  *----------------------------------------------------------------------------
  93  */
  94 VOID
  95 SetF15OrCacheFlushOnHaltRegister (
  96   IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
  97   IN       UINT64                       EntryPoint,
  98   IN       PLATFORM_CONFIGURATION       *PlatformConfig,
  99   IN       AMD_CONFIG_PARAMS            *StdHeader
 100   );
 101
 102 /*----------------------------------------------------------------------------------------
 103  *                          P U B L I C     F U N C T I O N S
 104  *----------------------------------------------------------------------------------------
 105  */
 106
 107 /* -----------------------------------------------------------------------------*/
 108 /**
 109  *    Enable Cpu Cache Flush On Halt Function
 110  *
 111  *    @param[in]       FamilySpecificServices   The current Family Specific Services.
 112  *    @param[in]       EntryPoint               Timepoint designator.
 113  *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
 114  *    @param[in]       StdHeader                Config Handle for library, services.
 115  */
 116 VOID
 117 SetF15OrCacheFlushOnHaltRegister (
 118   IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
 119   IN       UINT64                       EntryPoint,
 120   IN       PLATFORM_CONFIGURATION       *PlatformConfig,
 121   IN       AMD_CONFIG_PARAMS            *StdHeader
 122   )
 123 {
 124   UINT32       AndMask;
 125   UINT32       OrMask;
 126   PCI_ADDR     PciAddress;
 127
 128   if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
 129     // Set D18F3xDC[CacheFlushOnHaltCtl] != 0
 130     PciAddress.Address.Function = FUNC_3;
 131     PciAddress.Address.Register = CPTC2_REG;
 132     OrMask = 0;
 133     AndMask = 0xFC00FFFF;
 134     ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltCtl = 7;
 135     ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltTmr = 0x28;
 136     OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
 137
 138     PciAddress.Address.Function = FUNC_4;
 139     PciAddress.Address.Register = CSTATE_CTRL1_REG;
 140     OrMask = 0;
 141     AndMask = 0xFF11FF11;
 142     // D18F4x118[CpuPrbEnCstAct0] = 1
 143     // D18F4x118[CpuPrbEnCstAct1] = 1
 144     // D18F4x118[CacheFlushEnCstAct0] = 1
 145     ((CSTATE_CTRL1_REGISTER *) &OrMask)->CpuPrbEnCstAct0 = 1;
 146     ((CSTATE_CTRL1_REGISTER *) &OrMask)->CpuPrbEnCstAct1 = 1;
 147     ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct0 = 1;
 148
 149     // Set C-state Action Field 0
 150     ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushTmrSelCstAct0 = 2;
 151     // Set C-state Action Field 1
 152     ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct1 = 1;
 153     ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushTmrSelCstAct1 = 1;
 154
 155     OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x118
 156
 157     // D18F4x128[CacheFlushSucMonThreshold] = 0
 158     PciAddress.Address.Function = FUNC_4;
 159     PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG;
 160     OrMask = 0;
 161     AndMask = 0xFFFFFFFF;
 162     ((CSTATE_POLICY_CTRL1_REGISTER *) &AndMask)->CacheFlushSucMonThreshold = 0;
 163     OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x128
 164
 165     // D18F3x84[ClkDivisorSmafAct7] = 0
 166     // D18F3x84[CpuPrbEnSmafAct7]   = 1
 167     PciAddress.Address.Function = FUNC_3;
 168     PciAddress.Address.Register = ACPI_PWR_STATE_CTRL_HI_REG;
 169     OrMask = 0;
 170     AndMask = 0xFFFFFFFF;
 171     ((ACPI_PWR_STATE_CTRL_HI_REGISTER *) &AndMask)->ClkDivisorSmafAct7 = 0;
 172     ((ACPI_PWR_STATE_CTRL_HI_REGISTER *) &OrMask)->CpuPrbEnSmafAct7 = 1;
 173     OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x84
 174
 175     //Override the default setting
 176     IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
 177   }
 178 }
 179
 180 CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt =
 181 {
 182   0,
 183   SetF15OrCacheFlushOnHaltRegister
 184 };