5 * AMD Family_15 Models 0x00 - 0x0F Power Plane Initialization
7 * Performs the "BIOS Requirements for Power Plane Initialization" as described
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: CPU/Family/0x15/OR
13 * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
17 ******************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
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23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
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28 * documentation and/or other materials provided with the distribution.
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33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ******************************************************************************
47 /*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
54 #include "cpuRegisters.h"
55 #include "cpuF15PowerMgmt.h"
56 #include "cpuF15OrPowerMgmt.h"
57 #include "cpuApicUtilities.h"
58 #include "cpuServices.h"
59 #include "GeneralServices.h"
60 #include "cpuFamilyTranslation.h"
62 #include "OptionMultiSocket.h"
63 #include "F15OrPowerPlane.h"
68 #define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE
70 /*----------------------------------------------------------------------------------------
71 * D E F I N I T I O N S A N D M A C R O S
72 *----------------------------------------------------------------------------------------
75 /*----------------------------------------------------------------------------------------
76 * T Y P E D E F S A N D S T R U C T U R E S
77 *----------------------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------------------
81 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
82 *----------------------------------------------------------------------------------------
86 F15OrPmVrmLowPowerModeEnable (
87 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
88 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
89 IN PCI_ADDR PciAddress,
90 IN AMD_CONFIG_PARAMS *StdHeader
94 /*----------------------------------------------------------------------------------------
95 * E X P O R T E D F U N C T I O N S
96 *----------------------------------------------------------------------------------------
98 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
100 /*---------------------------------------------------------------------------------------*/
102 * Family 15h core 0 entry point for performing power plane initialization.
104 * The steps are as follows:
105 * 1. Configure D18F3xD8[VSRampSlamTime] based on platform
107 * 2. Configure F3xD4[PowerStepUp & PowerStepDown]
108 * 3. Optionally configure F3xA0[PsiVidEn & PsiVid]
110 * @param[in] FamilySpecificServices The current Family Specific Services.
111 * @param[in] CpuEarlyParams Service parameters
112 * @param[in] StdHeader Config handle for library and services.
116 F15OrPmPwrPlaneInit (
117 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
118 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
119 IN AMD_CONFIG_PARAMS *StdHeader
124 UINT32 LocalPciRegister;
127 PLATFORM_FEATS Features;
129 OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
130 GetCurrentCore (&Core, StdHeader);
133 // Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
134 // Before characterization has taken place, no calculations are necessary.
135 PciAddress.Address.Function = FUNC_3;
136 PciAddress.Address.Register = CPTC1_REG;
137 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
139 AndMask = 0xFFFFFFFF;
140 ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSRampSlamTime = 1;
141 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
143 // Configure PowerStepUp/PowerStepDown
144 PciAddress.Address.Register = CPTC0_REG;
145 AndMask = 0xFFFFFFFF;
146 ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
147 ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
149 Features.PlatformValue = 0;
150 GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
151 if (Features.PlatformFeatures.PlatformSingleLink == 1) {
152 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = 8;
153 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = 8;
155 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = 3;
156 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = 3;
158 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
160 if (IsWarmReset (StdHeader)) {
162 F15OrPmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader);
166 /*---------------------------------------------------------------------------------------*/
168 * Sets up PSI_L operation.
170 * This function implements the LowPowerThreshold parameter.
172 * @param[in] FamilySpecificServices The current Family Specific Services.
173 * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter.
174 * @param[in] PciAddress Segment, bus, device number of the node to transition.
175 * @param[in] StdHeader Config handle for library and services.
180 F15OrPmVrmLowPowerModeEnable (
181 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
182 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
183 IN PCI_ADDR PciAddress,
184 IN AMD_CONFIG_PARAMS *StdHeader
188 UINT32 PstateCurrent;
189 UINT32 NextPstateCurrent;
198 if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) {
200 PreviousVID = 0x7F; // Initialize to invalid zero volt VID code
202 PciAddress.Address.Function = FUNC_3;
203 PciAddress.Address.Register = CPTC2_REG;
204 LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
206 for (Pstate = 0; Pstate <= (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; Pstate++) {
207 if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) {
208 LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
209 PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid);
210 if ((Pstate + 1) > (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal) {
211 NextPstateCurrent = 0;
212 } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) {
213 NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit + NextPstateCurrent;
215 if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (PstateVID != PreviousVID)) {
219 PreviousVID = PstateVID;
223 PciAddress.Address.Function = FUNC_3;
224 PciAddress.Address.Register = PW_CTL_MISC_REG;
226 AndMask = 0xFFFFFFFF;
227 ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0;
229 ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID;
230 ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1;
232 ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0;
234 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader);