src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_15 Orochi PCI tables with values as defined in BKDG
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/Family/0x15/OR
  10  * @e \$Revision: 59564 $   @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "cpuRegisters.h"
  50 #include "Table.h"
  51 #include "Filecode.h"
  52 CODE_GROUP (G3_DXE)
  53 RDATA_GROUP (G3_DXE)
  54
  55 #define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE
  56
  57
  58 /*----------------------------------------------------------------------------------------
  59  *                   D E F I N I T I O N S    A N D    M A C R O S
  60  *----------------------------------------------------------------------------------------
  61  */
  62
  63 /*----------------------------------------------------------------------------------------
  64  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  65  *----------------------------------------------------------------------------------------
  66  */
  67
  68 /*----------------------------------------------------------------------------------------
  69  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  70  *----------------------------------------------------------------------------------------
  71  */
  72
  73 /*----------------------------------------------------------------------------------------
  74  *                          E X P O R T E D    F U N C T I O N S
  75  *----------------------------------------------------------------------------------------
  76  */
  77
  78 //  P C I    T a b l e s
  79 // ----------------------
  80
  81 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrPciRegisters[] =
  82 {
  83 // F0x68 - Link Transaction Control
  84 // bit[11]   , RespPassPW = 1
  85 // bits[14:13], BufRelPri = 1
  86 // bit[19:17], for 8bit APIC config
  87 // bit[22:21], DsNpReqLmt = 10b
  88 // bit [25] CHtExtAddrEn = 1
  89   {
  90     PciRegister,
  91     {
  92       AMD_FAMILY_15,                      // CpuFamily
  93       AMD_F15_OR_ALL                      // CpuRevision
  94     },
  95     {AMD_PF_ALL},                           // platformFeatures
  96     {{
  97       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
  98       0x024E2800,                           // regData
  99       0x026E6800,                           // regMask
 100     }}
 101   },
 102 // F0x6C - Link Initialization Control
 103 // bit[23] TxSSBusPwrSaveEn = 1
 104   {
 105     PciRegister,
 106     {
 107       AMD_FAMILY_15,                      // CpuFamily
 108       AMD_F15_OR_ALL                      // CpuRevision
 109     },
 110     {AMD_PF_ALL},                           // platformFeatures
 111     {{
 112       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
 113       0x00800000,                           // regData
 114       0x00800000,                           // regMask
 115     }}
 116   },
 117 // F0x[E4,A4,C4,84] Link Control Register
 118 // bit [15] Addr64bitEn = 1
 119   {
 120     HtHostPciRegister,
 121     {
 122       AMD_FAMILY_15,                      // CpuFamily
 123       AMD_F15_OR_ALL                      // CpuRevision
 124    },
 125     {AMD_PF_ALL},
 126     {{
 127       HT_HOST_FEAT_NONCOHERENT,
 128       0x4,
 129       0x00008000,
 130       0x00008000,
 131     }}
 132   },
 133 // F0x[E4,C4,A4,84] - Link 0 Control Register
 134 // bit[13] LdtStopTriEn = 1
 135   {
 136     HtHostPciRegister,
 137     {
 138       AMD_FAMILY_15,                      // CpuFamily
 139       AMD_F15_OR_ALL                      // CpuRevision
 140     },
 141     {AMD_PF_ALL},                           // platformFeatures
 142     {{
 143       HT_HOST_FEATURES_ALL,                 // link feats
 144       0x04,                                 // Address
 145       0x00002000,                           // regData
 146       0x00002000,                           // regMask
 147     }}
 148   },
 149 // F0x[E4,C4,A4,84] - Link 0 Control Register
 150 // bit [12] IsocEn = 0 default
 151   {
 152     HtHostPciRegister,
 153     {
 154       AMD_FAMILY_15,                      // CpuFamily
 155       AMD_F15_OR_ALL                      // CpuRevision
 156     },
 157     { (AMD_PF_NFCM | AMD_PF_UMA) },
 158     {{
 159       HT_HOST_FEATURES_ALL,                 // link feats
 160       0x04,                                 // Address
 161       0x00000000,                           // regData
 162       0x00001000,                           // regMask
 163     }}
 164   },
 165 // F0x[E4,C4,A4,84] - Link 0 Control Register
 166 // bit [12] IsocEn = 1 for Isochronous control flow modes.
 167   {
 168     HtHostPciRegister,
 169     {
 170       AMD_FAMILY_15,                      // CpuFamily
 171       AMD_F15_OR_ALL                      // CpuRevision
 172     },
 173     { (AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU) },
 174     {{
 175       HT_HOST_FEATURES_ALL,                 // link feats
 176       0x04,                                 // Address
 177       0x00001000,                           // regData
 178       0x00001000,                           // regMask
 179     }}
 180   },
 181 // F0x[F0,D0,B0,90] - Link Base Channel Buffer Count
 182 // bit[31] LockBc = 1
 183   {
 184     HtHostPciRegister,
 185     {
 186       AMD_FAMILY_15,                      // CpuFamily
 187       AMD_F15_OR_ALL                      // CpuRevision
 188     },
 189     {AMD_PF_ALL},                           // platformFeatures
 190     {{
 191       HT_HOST_FEATURES_ALL,                 // link feats
 192       0x10,                                 // Address
 193       0x80000000,                           // regData
 194       0x80000000,                           // regMask
 195     }}
 196   },
 197 // F0x150 - Link Global Retry Control Register
 198 // bit[18:16] TotalRetryAttempts = 7
 199 // bit[13] HtRetryCrcDatInsDynEn = 1
 200 // bit[12]HtRetryCrcCmdPackDynEn = 1
 201 // bit[11:9] HtRetryCrcDatIns = leave default reset value (erratum #600)
 202 // bit[8] HtRetryCrcCmdPack = 1
 203   {
 204     PciRegister,
 205     {
 206       AMD_FAMILY_15,                      // CpuFamily
 207       AMD_F15_OR_ALL                      // CpuRevision
 208     },
 209     {AMD_PF_ALL},                           // platformFeatures
 210     {{
 211       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
 212       0x00073100,                           // regData
 213       0x00073100,                           // regMask
 214     }}
 215   },
 216 // F0x16C - Link Global Extended Control Register
 217 // bit[22:17] FullT0Time = 0x33
 218 // bit[15:13] ForceFullT0 = 7
 219 // bit[7:6] InLnSt = 01b (PHY_OFF)
 220 // bit[5:0] T0Time = 0x26
 221   {
 222     PciRegister,
 223     {
 224       AMD_FAMILY_15,                      // CpuFamily
 225       AMD_F15_OR_ALL                      // CpuRevision
 226     },
 227     {AMD_PF_ALL},                           // platformFeatures
 228     {{
 229       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
 230       0x0066E066,                           // regData
 231       0x007EE0FF,                           // regMask
 232     }}
 233   },
 234 // F0x[18C:170] - Link Extended Control Register - All connected links.
 235 // bit[8] LS2En = 1
 236   {
 237     HtLinkPciRegister,
 238     {
 239       AMD_FAMILY_15,                      // CpuFamily
 240       AMD_F15_OR_ALL                      // CpuRevision
 241     },
 242     {AMD_PF_ALL},                           // platform Features
 243     {{
 244       HT_HOST_FEATURES_ALL,
 245       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
 246       0x00000100,                           // regData
 247       0x00000100,                           // regMask
 248     }}
 249   },
 250 // F2x1B0 - Extended Memory Controller Configuration Low
 251 // bits[10:8], CohPrefPrbLmt = 0
 252   {
 253     ProfileFixup,
 254     {
 255       AMD_FAMILY_15,                        // CpuFamily
 256       AMD_F15_OR_ALL                        // CpuRevision
 257     },
 258     {AMD_PF_ALL},                             // platformFeatures
 259     {{
 260       PERFORMANCE_PROBEFILTER,              // Features
 261       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
 262       0x00000000,                           // regData
 263       0x00000700,                           // regMask
 264     }}
 265   },
 266 // Function 3 - Misc. Control
 267
 268 // F3x40 - MCA NB Control
 269 //
 270 // bit[8], MstrAbrtEn = 1
 271   {
 272     PciRegister,
 273     {
 274       AMD_FAMILY_15,                      // CpuFamily
 275       AMD_F15_OR_ALL                      // CpuRevision
 276     },
 277     {AMD_PF_ALL},                           // platformFeatures
 278     {{
 279       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40),  // Address
 280       0x00000100,                           // regData
 281       0x00000100,                           // regMask
 282     }}
 283   },
 284 // F3x44 - MCA NB Configuration
 285 // bit[30]  SyncOnDramAdrParErrEn = 1
 286 // bit[27]  NB MCA to Master CPU Enable = 1
 287 // bit[25]  DisPciCfgCpuErrRsp = 1
 288 // bit[21]  SyncFloodOnAnyUcErr = 1
 289 // bit[20]  SyncOnWDTEn = 1
 290 // bit[6]   CpuErrDis = 1
 291 // bit[4]   SyncPktPropDis = 0
 292 // bit[3]   SyncPktGenDis = 0
 293 // bit[2]   SyncOnUcEccEn = 1
 294   {
 295     PciRegister,
 296     {
 297       AMD_FAMILY_15,                      // CpuFamily
 298       AMD_F15_OR_ALL                      // CpuRevision
 299     },
 300     {AMD_PF_ALL},                           // platformFeatures
 301     {{
 302       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
 303       0x4A300044,                           // regData
 304       0x4A30005C,                           // regMask
 305     }}
 306   },
 307 // F3x70 - SRI_to_XBAR Command Buffer Count
 308 // bits[30:28] IsocRspCBC = 1
 309 // bits[26:24] IsocPreqCBC = 0
 310 // bits[22:20] IsocReqCBC = 1
 311 // bits[18:16] UpRspCBC = 7
 312 // bits[14:12] DnPreqCBC = 1
 313 // bits[10:8]  UpPreqCBC = 1
 314 // bits[7:6]   DnRspCBC = 1
 315 // bits[5:4]   DnReqCBC = 1
 316 // bits[2:0]   UpReqCBC = 5
 317   {
 318     PciRegister,
 319     {
 320       AMD_FAMILY_15,                      // CpuFamily
 321       AMD_F15_OR_ALL                      // CpuRevision
 322     },
 323     {AMD_PF_ALL},                           // platformFeatures
 324     {{
 325       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 326       0x10171155,                           // regData
 327       0x777777F7,                           // regMask
 328     }}
 329   },
 330 // F3x74 - XBAR_to_SRI Command Buffer Count
 331 // bits[31:28] DRReqCBC = 0
 332 // bits[26:24] IsocPreqCBC = 0
 333 // bits[23:20] IsocReqCBC = 1
 334 // bits[19:16] ProbeCBC = 7
 335 // bits[14:12] DnPreqCBC = 2
 336 // bits[10:8]  UpPreqCBC = 1
 337 // bits[6:4]   DnReqCBC = 1
 338 // bits[2:0]   UpReqCBC = 1
 339   {
 340     ProfileFixup,
 341     {
 342       AMD_FAMILY_15,                      // CpuFamily
 343       AMD_F15_OR_ALL                      // CpuRevision
 344     },
 345     {AMD_PF_ALL},                           // platformFeatures
 346     {{
 347       PERFORMANCE_L3_CACHE,                 // Features
 348       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 349       0x00172111,                           // regData
 350       0xF7FF7777,                           // regMask
 351     }}
 352   },
 353 // F3x78 - MCT to XBAR Buffer Count
 354 // bits[12:8]  ProbeCBC = 0Eh
 355 // bits[4:0]   RspCBC = 12h
 356   {
 357     ProfileFixup,
 358     {
 359       AMD_FAMILY_15,                      // CpuFamily
 360       AMD_F15_OR_ALL                      // CpuRevision
 361     },
 362     {AMD_PF_ALL},                           // platformFeatures
 363     {{
 364       PERFORMANCE_PROFILE_ALL,              // Features
 365       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78),  // Address
 366       0x00000E12,                           // regData
 367       0x00001F1F,                           // regMask
 368     }}
 369   },
 370 // F3x78 - MCT to XBAR Buffer Count
 371 // bits[12:8]  ProbeCBC = 0Ch
 372 // bits[4:0]   RspCBC = 14h
 373   {
 374     ProfileFixup,
 375     {
 376       AMD_FAMILY_15,                      // CpuFamily
 377       AMD_F15_OR_ALL                      // CpuRevision
 378     },
 379     {AMD_PF_ALL},                           // platformFeatures
 380     {{
 381       PERFORMANCE_PROBEFILTER,              // Features
 382       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78),  // Address
 383       0x00000C14,                           // regData
 384       0x00001F1F,                           // regMask
 385     }}
 386   },
 387 // F3x7C - Free List Buffer Count
 388 // bits[26:23] SrqExtFreeListBC = 8
 389 // bits[22:20] Sri2XbarFreeRspDBC = 0
 390 // bits[19:16] Sri2XbarFreeXreqDBC = 0xD
 391 // bits[15:12] Sri2XbarFreeRspCBC = 0
 392 // bits[11:8]  Sri2XbarFreeXreqCBC = 0xF
 393   {
 394     PciRegister,
 395     {
 396       AMD_FAMILY_15,                      // CpuFamily
 397       AMD_F15_OR_ALL                      // CpuRevision
 398     },
 399     {AMD_PF_ALL},                           // platformFeatures
 400     {{
 401       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
 402       0x040D0F00,                           // regData
 403       0x07FFFF00,                           // regMask
 404     }}
 405   },
 406 // F3x7C - Free List Buffer Count
 407 // bits[4:0]   Xbar2SriFreeListCBC = 0x16
 408   {
 409     ProfileFixup,
 410     {
 411       AMD_FAMILY_15,                      // CpuFamily
 412       AMD_F15_OR_ALL                      // CpuRevision
 413     },
 414     {AMD_PF_ALL},                           // platformFeatures
 415     {{
 416       PERFORMANCE_L3_CACHE,                 // Features
 417       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),               // Address
 418       0x00000016,                           // regData
 419       0x0000001F,                           // regMask
 420     }}
 421   },
 422 // F3x80 - ACPI Power State Control
 423 // ACPI State C2
 424 // bit[0] CpuPrbEn = 1
 425 // bit[1] NbLowPwrEn = 0
 426 // bit[2] NbGateEn = 0
 427 // bits[7:5] ClkDivisor = 4
 428 // ACPI State C3, C1E or Link init
 429 // bit[0] CpuPrbEn = 0
 430 // bit[1] NbLowPwrEn = 1
 431 // bit[2] NbGateEn = 0
 432 // bit[3] NbCofChg = 0
 433 // bit[4] Reserved = 0
 434 // bits[7:5] ClkDivisor = 7
 435 // NB P-state changes
 436 // bit[0] CpuPrbEn = 1
 437 // bit[1] NbLowPwrEn = 1
 438 // bit[2] NbGateEn = 0
 439 // bit[3] NbCofChg = 1
 440 // bit[4] Reserved = 0
 441 // bits[7:5] ClkDivisor = 0
 442 // S1
 443 // bit[0] CpuPrbEn = 0
 444 // bit[1] NbLowPwrEn = 1
 445 // bit[2] NbGateEn = 0
 446 // bit[3] NbCofChg = 0
 447 // bit[4] Reserved = 0
 448 // bits[7:5] ClkDivisor = 7
 449   {
 450     PciRegister,
 451     {
 452       AMD_FAMILY_15,                        // CpuFamily
 453       AMD_F15_OR_ALL                        // CpuRevision
 454     },
 455     {AMD_PF_ALL},                             // platformFeatures
 456     {{
 457       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 458       0xE20BE281,                           // regData
 459       0xFFFFFFE7,                           // regMask
 460     }}
 461   },
 462 // F3x84 - ACPI Power State Control
 463 // ACPI State S3
 464 // bit[0] CpuPrbEn = 0
 465 // bit[1] NbLowPwrEn = 1
 466 // bit[2] NbGateEn = 0
 467 // bit[3] NbCofChg = 0
 468 // bit[4] Reserved = 0
 469 // bits[7:5] ClkDivisor = 7
 470 // ACPI State S4/S5
 471 // bit[0] CpuPrbEn = 0
 472 // bit[1] NbLowPwrEn = 1
 473 // bit[2] NbGateEn = 0
 474 // bit[3] NbCofChg = 0
 475 // bit[4] Reserved = 0
 476 // bits[7:5] ClkDivisor = 7
 477 // ACPI State C1
 478 // bit[0] CpuPrbEn = 0
 479 // bit[1] NbLowPwrEn = 0
 480 // bit[2] NbGateEn = 0
 481 // bit[3] NbCofChg = 0
 482 // bit[4] Reserved = 0
 483 // bits[7:5] ClkDivisor = 7
 484   {
 485     PciRegister,
 486     {
 487       AMD_FAMILY_15,                      // CpuFamily
 488       AMD_F15_OR_ALL                      // CpuRevision
 489     },
 490     {AMD_PF_ALL},                           // platformFeatures
 491     {{
 492       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
 493       0xE0E200E2,                           // regData
 494       0xEFFF00FF,                           // regMask
 495     }}
 496   },
 497 // F3x84 - ACPI Power State Control
 498 // ACPI State C1
 499 // bits[0] CpuPrbEn = 0
 500 // bits[1] NbLowPwrEn = 0
 501 // bits[2] NbGateEn = 0
 502 // bits[7:5] ClkDivisor = 4
 503   {
 504     PciRegister,
 505     {
 506       AMD_FAMILY_15,                      // CpuFamily
 507       AMD_F15_OR_ALL                      // CpuRevision
 508     },
 509     {AMD_PF_SINGLE_CORE},                   // platformFeatures
 510     {{
 511       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
 512       0x80000000,                           // regData
 513       0xE7000000,                           // regMask
 514     }}
 515   },
 516 // F3x90 - GART Aperture Control
 517 // bit[6] = DisGartTblWlkPrb, Erratum 540
 518   {
 519     PciRegister,
 520     {
 521       AMD_FAMILY_15,                        // CpuFamily
 522       AMD_F15_OR_ALL                        // CpuRevision
 523     },
 524     {AMD_PF_ALL},                             // platformFeatures
 525     {{
 526       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x90),  // Address
 527       0x00000040,                           // regData
 528       0x00000040,                           // regMask
 529     }}
 530   },
 531 // F3xA0 - Power Control Miscellaneous
 532 // bit[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
 533   {
 534     ProfileFixup,
 535     {
 536       AMD_FAMILY_15,                        // CpuFamily
 537       AMD_F15_OR_ALL                        // CpuRevision
 538     },
 539     {AMD_PF_ALL},                             // platformFeatures
 540     {{
 541       PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
 542       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
 543       0x00000200,                           // regData
 544       0x00000200,                           // regMask
 545     }}
 546   },
 547 // F3xD4 - Clock Power Timing Control 0
 548 // bits[11:8] ClkRampHystSel = 0xF
 549 // bits[15] StutterScrubEn = 0
 550 // bits[14] CacheFlushImmOnAllHalt = 0
 551 // bits[13] MTC1eEn = 0
 552 // bits[17:16] LnkPllLock = 1
 553 // bits[30:28] NbClkDiv = 4
 554 // bits[31] NbClkDivApplyAll = 1
 555   {
 556     PciRegister,
 557     {
 558       AMD_FAMILY_15,                      // CpuFamily
 559       AMD_F15_OR_ALL                      // CpuRevision
 560     },
 561     {AMD_PF_ALL},                           // platformFeatures
 562     {{
 563       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
 564       0xC0010F00,                           // regData
 565       0xF003EF00,                           // regMask
 566     }}
 567   },
 568 // F3xD8 - Clock Power Timing Control 1
 569 // bits[6:4]   VSRampSlamTime = 1
 570 // bits[27:24] ReConDel = 3
 571   {
 572     PciRegister,
 573     {
 574       AMD_FAMILY_15,                      // CpuFamily
 575       AMD_F15_OR_ALL                      // CpuRevision
 576     },
 577     {AMD_PF_ALL},                           // platformFeatures
 578     {{
 579       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8),  // Address
 580       0x03000010,                           // regData
 581       0x0F000070,                           // regMask
 582     }}
 583   },
 584 // F3x140 - SRI_to_XCS Token Count
 585 // bits[1:0]   UpReqTok = 1
 586 // bits[3:2]   DnReqTok = 1
 587 // bits[5:4]   UpPreqTok = 1
 588 // bits[7:6]   DnPreqTok = 1
 589 // bits[11:10] DnRspTok = 1
 590 // bits[13:12] IsocReqTok = 1
 591 // bits[15:14] IsocPreqTok = 0
 592 // bits[17:16] IsocRspTok = 1
 593   {
 594     PciRegister,
 595     {
 596       AMD_FAMILY_15,                      // CpuFamily
 597       AMD_F15_OR_ALL                      // CpuRevision
 598     },
 599     {AMD_PF_ALL},                           // platform Features
 600     {{
 601       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 602       0x00011455,                           // regData
 603       0x0003FCFF,                           // regMask
 604     }}
 605   },
 606 // F3x144 - MCT to XCS Token Count
 607 // bits[3:0] RspTok = 5
 608 // bits[7:4] ProbeTok = 5
 609   {
 610     ProfileFixup,
 611     {
 612       AMD_FAMILY_15,                      // CpuFamily
 613       AMD_F15_OR_ALL                      // CpuRevision
 614     },
 615     {AMD_PF_ALL},                           // platformFeatures
 616     {{
 617       PERFORMANCE_PROFILE_ALL,
 618       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 619       0x00000055,                           // regData
 620       0x000000FF,                           // regMask
 621     }}
 622   },
 623 // F3x144 - MCT to XCS Token Count
 624 // bits[3:0] RspTok = 8
 625 // bits[7:4] ProbeTok = 2
 626   {
 627     ProfileFixup,
 628     {
 629       AMD_FAMILY_15,                      // CpuFamily
 630       AMD_F15_OR_ALL                      // CpuRevision
 631     },
 632     {AMD_PF_ALL},                           // platformFeatures
 633     {{
 634       PERFORMANCE_PROBEFILTER,              // Features
 635       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
 636       0x00000028,                           // regData
 637       0x000000FF,                           // regMask
 638     }}
 639   },
 640 // F3x160 - NB Machine Check Misc 0
 641 // bits[23:20] LvtOffset = 1
 642   {
 643     PciRegister,
 644     {
 645       AMD_FAMILY_15,                      // CpuFamily
 646       AMD_F15_OR_ALL                      // CpuRevision
 647     },
 648     {AMD_PF_ALL},                           // platformFeatures
 649     {{
 650       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x160), // Address
 651       0x00100000,                           // regData
 652       0x00F00000,                           // regMask
 653     }}
 654   },
 655 // F3x168 - NB Machine Check Misc 1
 656 // bits[23:20] LvtOffset = 1
 657   {
 658     PciRegister,
 659     {
 660       AMD_FAMILY_15,                      // CpuFamily
 661       AMD_F15_OR_ALL                      // CpuRevision
 662     },
 663     {AMD_PF_ALL},                           // platformFeatures
 664     {{
 665       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x168), // Address
 666       0x00100000,                           // regData
 667       0x00F00000,                           // regMask
 668     }}
 669   },
 670 // F3x170 - NB Machine Check Misc 2
 671 // bits[23:20] LvtOffset = 1
 672   {
 673     PciRegister,
 674     {
 675       AMD_FAMILY_15,                      // CpuFamily
 676       AMD_F15_OR_ALL                      // CpuRevision
 677     },
 678     {AMD_PF_ALL},                           // platformFeatures
 679     {{
 680       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x170), // Address
 681       0x00100000,                           // regData
 682       0x00F00000,                           // regMask
 683     }}
 684   },
 685 // F3x180 - NB Extended Configuration
 686 // bit[1]  SyncFloodOnUsPwDatErr = 1
 687 // bit[5]  DisPciCfgCpuMstAbtRsp = 1
 688 // bit[6]  SyncFloodOnDatErr = 1
 689 // bit[7]  SyncFloodOnTgtAbtErr = 1
 690 // bit[8]  SyncFloodOnHtProtEn = 1
 691 // bit[9]  SyncOnUCNbAryEn = 1
 692 // bit[20] SyncFloodOnL3LeakErr = 1
 693 // bit[21] SyncFloodOnCpuLeakErr = 1
 694 // bit[22] SyncFloodOnTblWalkErr = 1
 695 // bit[24] McaLogErrAddrWdtErr = 1
 696   {
 697     PciRegister,
 698     {
 699       AMD_FAMILY_15,                      // CpuFamily
 700       AMD_F15_OR_ALL                      // CpuRevision
 701     },
 702     {AMD_PF_ALL},                           // platformFeatures
 703     {{
 704       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
 705       0x017003E2,                           // regData
 706       0x017003E2,                           // regMask
 707     }}
 708   },
 709 // F3x188 - NB Configuration 2 Register
 710 // bit[9]  DisL3HiPriFreeListAlloc = 1
 711   {
 712     PciRegister,
 713     {
 714       AMD_FAMILY_15,                        // CpuFamily
 715       AMD_F15_OR_ALL                        // CpuRevision
 716     },
 717     {AMD_PF_ALL},                             // platformFeatures
 718     {{
 719       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
 720       0x00000200,                           // regData
 721       0x00000200,                           // regMask
 722     }}
 723   },
 724 // F3x1A0 - L3 Buffer Count
 725 // bits[17:16] CpuToNbFreeBufCnt = 3
 726   {
 727     ProfileFixup,
 728     {
 729       AMD_FAMILY_15,                      // CpuFamily
 730       AMD_F15_OR_ALL                      // CpuRevision
 731     },
 732     {AMD_PF_ALL},                           // platformFeatures
 733     {{
 734       PERFORMANCE_L3_CACHE,                 // Features
 735       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
 736       0x00030000,                           // regData
 737       0x00030000,                           // regMask
 738     }}
 739   },
 740 // F3x1B8 - L3 Control 1
 741 // bit[12] L3PrivReplEn = 1
 742 // bit[18] Reserved = 1, Erratum #504
 743   {
 744     ProfileFixup,
 745     {
 746       AMD_FAMILY_15,                      // CpuFamily
 747       AMD_F15_OR_ALL                      // CpuRevision
 748     },
 749     {AMD_PF_ALL},                           // platformFeatures
 750     {{
 751       PERFORMANCE_L3_CACHE,                 // Features
 752       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
 753       0x00041000,                           // regData
 754       0x00041000,                           // regMask
 755     }}
 756   },
 757 // F3x1E4 - SBI Control
 758 // bits[11:8] LvtOffset = 3
 759   {
 760     PciRegister,
 761     {
 762       AMD_FAMILY_15,                      // CpuFamily
 763       AMD_F15_OR_ALL                      // CpuRevision
 764     },
 765     {AMD_PF_ALL},                           // platformFeatures
 766     {{
 767       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1E4), // Address
 768       0x00000300,                           // regData
 769       0x00000F00,                           // regMask
 770     }}
 771   },
 772 // F4x104 - TDP Accumulator Divisor Control
 773 // bits[1:0] TdpAccDivVal = 1
 774 // bits[13:2] TdpAccDivRate = 0x0C8
 775   {
 776     PciRegister,
 777     {
 778       AMD_FAMILY_15,                      // CpuFamily
 779       AMD_F15_OR_ALL                      // CpuRevision
 780     },
 781     {AMD_PF_ALL},                           // platformFeatures
 782     {{
 783       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address
 784       0x00000321,                           // regData
 785       0x00003FFF,                           // regMask
 786     }}
 787   },
 788 // F4x110 - Sample and Residency Timer
 789 // bits[11:0] CSampleTimer = 1
 790   {
 791     PciRegister,
 792     {
 793       AMD_FAMILY_15,                      // CpuFamily
 794       AMD_F15_OR_ALL                      // CpuRevision
 795     },
 796     {AMD_PF_ALL},                           // platformFeatures
 797     {{
 798       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address
 799       0x00000001,                           // regData
 800       0x00000FFF,                           // regMask
 801     }}
 802   },
 803 // F4x118 - C-state Control 1
 804 // bit [0]     CpuPrbEnCstAct0 = 0
 805 // bit [1]     CacheFlushEnCstAct0 = 0
 806 // bits[3:2]   CacheFlushTmrSelCstAct0 = 0
 807 // bits[7:5]   ClkDivisorCstAct0 = 0
 808 // bit [8]     PwrGateEnCstAct0 = 0
 809 // bit [16]    CpuPrbEnCstAct1 = 0
 810 // bit [17]    CacheFlushEnCstAct1 = 0
 811 // bits[19:18] CacheFlushTmrSelCstAct1 = 0
 812 // bits[23:21] ClkDivisorCstAct1 = 0
 813 // bit [24]    PwrGateEnCstAct1 = 0
 814   {
 815     PciRegister,
 816     {
 817       AMD_FAMILY_15,                      // CpuFamily
 818       AMD_F15_OR_ALL                      // CpuRevision
 819     },
 820     {AMD_PF_ALL},                           // platformFeatures
 821     {{
 822       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
 823       0x00000000,                           // regData
 824       0x01EF01EF,                           // regMask
 825     }}
 826   },
 827 // F4x11C - C-state Control 2
 828 // bit [0]     CpuPrbEnCstAct2 = 0
 829 // bit [1]     CacheFlushEnCstAct2 = 0
 830 // bits[3:2]   CacheFlushTmrSelCstAct2 = 0
 831 // bits[7:5]   ClkDivisorCstAct2 = 0
 832 // bit [8]     PwrGateEnCstAct2 = 0
 833   {
 834     PciRegister,
 835     {
 836       AMD_FAMILY_15,                      // CpuFamily
 837       AMD_F15_OR_ALL                      // CpuRevision
 838     },
 839     {AMD_PF_ALL},                           // platformFeatures
 840     {{
 841       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x11C), // Address
 842       0x00000000,                           // regData
 843       0x000001EF,                           // regMask
 844     }}
 845   },
 846 // F4x128 - C-state Policy Control 1
 847 // bits[20:18] CacheFlushSucMonThreshold = 4
 848 // bits[11:5]  CacheFlushTmr = 0x28
 849   {
 850     PciRegister,
 851     {
 852       AMD_FAMILY_15,                      // CpuFamily
 853       AMD_F15_OR_ALL                      // CpuRevision
 854     },
 855     {AMD_PF_ALL},                           // platformFeatures
 856     {{
 857       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x128), // Address
 858       0x00100500,                           // regData
 859       0x001C0FE0,                           // regMask
 860     }}
 861   },
 862 // F4x16C - APM TDP Control
 863 // bit[4] ApmTdpLimitIntEn = 1
 864   {
 865     PciRegister,
 866     {
 867       AMD_FAMILY_15,                      // CpuFamily
 868       AMD_F15_OR_ALL                      // CpuRevision
 869     },
 870     {AMD_PF_ALL},                           // platformFeatures
 871     {{
 872       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address
 873       0x00000010,                           // regData
 874       0x00000010,                           // regMask
 875     }}
 876   },
 877 // F4x1C4 - L3 Power Control Register
 878 // bits[8] L3PwrSavEn = 1
 879   {
 880     ProfileFixup,
 881     {
 882       AMD_FAMILY_15,                      // CpuFamily
 883       AMD_F15_OR_ALL                      // CpuRevision
 884     },
 885     {AMD_PF_ALL},                           // platformFeatures
 886     {{
 887       PERFORMANCE_L3_CACHE,                 // Features
 888       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
 889       0x00000100,                           // regData
 890       0x00000100,                           // regMask
 891     }}
 892   },
 893 // F4x1CC - L3 Control 2
 894 // bit[4]    ImplRdAnySubUnavail = 1
 895 // bits[8:6] ImplRdProjDelayThresh = 2
 896   {
 897     PciRegister,
 898     {
 899       AMD_FAMILY_15,                      // CpuFamily
 900       AMD_F15_OR_ALL                      // CpuRevision
 901     },
 902     {AMD_PF_ALL},                           // platformFeatures
 903     {{
 904       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1CC), // Address
 905       0x00000090,                           // regData
 906       0x000001D0,                           // regMask
 907     }}
 908   },
 909 // F5x88 - Northbridge Configuration 4
 910 // bit[5] Reserved, BIOS must set
 911   {
 912     ProfileFixup,
 913     {
 914       AMD_FAMILY_15,                      // CpuFamily
 915       AMD_F15_OR_ALL                      // CpuRevision
 916     },
 917     {AMD_PF_ALL},                           // platformFeatures
 918     {{
 919       0x04,                                 // Features
 920       MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88),  // Address
 921       0x00000020,                           // regData
 922       0x00000020,                           // regMask
 923     }}
 924   },
 925 // F5x88 - Northbridge Configuration 4
 926 // bit[14] Reserved, BIOS must set
 927   {
 928     PciRegister,
 929     {
 930       AMD_FAMILY_15,                      // CpuFamily
 931       AMD_F15_OR_Bx                       // CpuRevision
 932     },
 933     {AMD_PF_ALL},                           // platformFeatures
 934     {{
 935       MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88),  // Address
 936       0x00004000,                           // regData
 937       0x00004000,                           // regMask
 938     }}
 939   },
 940 // F5xE0 - Processor TDP Running Average
 941 // bits[3:0] RunAvgRange = 0xE
 942   {
 943     PciRegister,
 944     {
 945       AMD_FAMILY_15,                      // CpuFamily
 946       AMD_F15_OR_ALL                      // CpuRevision
 947     },
 948     {AMD_PF_ALL},                           // platformFeatures
 949     {{
 950       MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address
 951       0x0000000E,                           // regData
 952       0x0000000F,                           // regMask
 953     }}
 954   }
 955 };
 956
 957 CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable = {
 958   PrimaryCores,
 959   (sizeof (F15OrPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
 960   F15OrPciRegisters,
 961 };
 962