src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_15 Orochi PCI tables from Multi-Link BKDG paragraph recommended settings.
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/Family/0x15/OR
  10  * @e \$Revision: 41897 $   @e \$Date: 2010-11-12 12:39:18 +0800 (Fri, 12 Nov 2010) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "Ids.h"
  50 #include "cpuRegisters.h"
  51 #include "Table.h"
  52 #include "Filecode.h"
  53 #include "F15PackageType.h"
  54 CODE_GROUP (G3_DXE)
  55 RDATA_GROUP (G3_DXE)
  56
  57 #define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE
  58
  59
  60 /*----------------------------------------------------------------------------------------
  61  *                   D E F I N I T I O N S    A N D    M A C R O S
  62  *----------------------------------------------------------------------------------------
  63  */
  64
  65 /*----------------------------------------------------------------------------------------
  66  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  67  *----------------------------------------------------------------------------------------
  68  */
  69
  70 /*----------------------------------------------------------------------------------------
  71  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  72  *----------------------------------------------------------------------------------------
  73  */
  74
  75 /*----------------------------------------------------------------------------------------
  76  *                          E X P O R T E D    F U N C T I O N S
  77  *----------------------------------------------------------------------------------------
  78  */
  79
  80 //  P C I    T a b l e s
  81 // ----------------------
  82
  83 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrMultiLinkPciRegisters[] =
  84 {
  85   // Function 0
  86
  87 // F0x68 - Link Transaction Control
  88 // bit[14:13], BufRelPri = 01h
  89   {
  90     PciRegister,
  91     {
  92       AMD_FAMILY_15,                        // CpuFamily
  93       AMD_F15_OR_ALL,                          // CpuRevision  rev C or less.
  94     },
  95     {AMD_PF_MULTI_LINK},                      // platformFeatures
  96     {{
  97       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
  98       0x00002000,                           // regData
  99       0x00006000,                           // regMask
 100     }}
 101   },
 102   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 103   // 27:25 FreeData: 0
 104   // 24:20 FreeCmd: 8
 105   // 19:18 RspData: 3
 106   // 17:16 NpReqData: 3
 107   // 15:12 ProbeCmd: 8
 108   // 11:8 RspCmd: 9
 109   // 7:5 PReq: 2
 110   // 4:0 NpReqCmd: 4
 111 {
 112     HtHostPciRegister,
 113     {
 114       AMD_FAMILY_15,                      // CpuFamily
 115       AMD_F15_OR_ALL                         // CpuRevision
 116     },
 117     {AMD_PF_MULTI_LINK},  // platformFeatures
 118     {{
 119       HT_HOST_FEAT_COHERENT, // link features
 120       0x10,                               // address
 121       0x008F8944,                         // data
 122       0x0FFFFFFF                          // mask
 123     }}
 124   },
 125   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 126   // 27:25 FreeData: 0
 127   // 24:20 FreeCmd: 8
 128   // 19:18 RspData: 1
 129   // 17:16 NpReqData: 0
 130   // 15:12 ProbeCmd: 0
 131   // 11:8 RspCmd: 2
 132   // 7:5 PReq: 7
 133   // 4:0 NpReqCmd: 14
 134   {
 135     HtHostPciRegister,
 136     {
 137       AMD_FAMILY_15,                      // CpuFamily
 138       AMD_F15_OR_ALL                         // CpuRevision
 139     },
 140     {AMD_PF_MULTI_LINK},  // platformFeatures
 141     {{
 142       (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // link features
 143       0x10,                               // address
 144       0x008402EE,                         // data
 145       0x0FFFFFFF                          // mask
 146     }}
 147   },
 148   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 149   // 27:25 FreeData: 0
 150   // 24:20 FreeCmd: 8
 151   // 19:18 RspData: 3
 152   // 17:16 NpReqData: 3
 153   // 15:12 ProbeCmd: 4
 154   // 11:8 RspCmd: 9
 155   // 7:5 PReq: 2
 156   // 4:0 NpReqCmd: 8
 157   {
 158     HtHostPerfPciRegister,
 159     {
 160       AMD_FAMILY_15,                      // CpuFamily
 161       AMD_F15_OR_ALL                         // CpuRevision
 162     },
 163     {AMD_PF_MULTI_LINK},                    // platformFeatures
 164     {{
 165       PERFORMANCE_PROBEFILTER,
 166       HT_HOST_FEAT_COHERENT,              // link features
 167       0x10,                               // address
 168       0x008F4948,                         // data
 169       0x0FFFFFFF                          // mask
 170     }}
 171   },
 172   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 173   // 28:27 IsocRspData: 0
 174   // 26:25 IsocNpReqData: 0
 175   // 24:22 IsocRspCmd: 0
 176   // 21:19 IsocPReq: 0
 177   // 18:16 IsocNpReqCmd: 1
 178   {
 179     HtHostPciRegister,
 180     {
 181       AMD_FAMILY_15,                      // CpuFamily
 182       AMD_F15_OR_ALL                         // CpuRevision
 183     },
 184     {AMD_PF_MULTI_LINK},  // platformFeatures
 185     {{
 186       HT_HOST_FEAT_COHERENT,              // link features
 187       0x14,                               // address
 188       0x00010000,                         // data
 189       0x1FFF0000                          // mask
 190     }}
 191   },
 192   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 193   // 28:27 IsocRspData: 0
 194   // 26:25 IsocNpReqData: 0
 195   // 24:22 IsocRspCmd: 0
 196   // 21:19 IsocPReq: 0
 197   // 18:16 IsocNpReqCmd: 1
 198   {
 199     HtHostPciRegister,
 200     {
 201       AMD_FAMILY_15,                        // CpuFamily
 202       AMD_F15_OR_ALL                           // CpuRevision
 203     },
 204     {AMD_PF_MULTI_LINK},
 205     {{
 206       (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features
 207       0x14,                                 // Address
 208       0x00010000,                           // Data
 209       0x1FFF0000                            // Mask
 210     }},
 211   },
 212
 213 // Function 3 - Misc. Control
 214
 215 // NOTE: Order is important. Do not re-order
 216 // the entries for F3x140.
 217
 218 // F3x140 - SRI_to_XCS Token Count
 219 // bits[9:8] UpRspTok = 3
 220 // bits[23:20] FreeTok = 10
 221   {
 222     TokenPciRegister,
 223     {
 224       AMD_FAMILY_15,                        // CpuFamily
 225       AMD_F15_OR_ALL                           // CpuRevision
 226     },
 227     {AMD_PF_MULTI_LINK},                      // platformFeatures
 228     {{
 229       PERFORMANCE_PROFILE_ALL,
 230       (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // SCM
 231       PACKAGE_TYPE_SCM,
 232       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 233       0x00A00300,                           // regData
 234       0x00F00300,                           // regMask
 235     }}
 236   },
 237 // F3x140 - SRI_to_XCS Token Count
 238 // bits[9:8] UpRspTok = 3
 239 // bits[23:20] FreeTok = 10
 240   {
 241     TokenPciRegister,
 242     {
 243       AMD_FAMILY_15,                        // CpuFamily
 244       AMD_F15_OR_ALL                           // CpuRevision
 245     },
 246     {AMD_PF_MULTI_LINK},                      // platformFeatures
 247     {{
 248       PERFORMANCE_PROFILE_ALL,
 249       (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // MCM1 or MCM2h
 250       PACKAGE_TYPE_MCM,
 251       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 252       0x00A00300,                           // regData
 253       0x00F00300,                           // regMask
 254     }}
 255   },
 256 // F3x140 - SRI_to_XCS Token Count
 257 // bits[9:8] UpRspTok = 3
 258 // bits[23:20] FreeTok = 9
 259   {
 260     TokenPciRegister,
 261     {
 262       AMD_FAMILY_15,                        // CpuFamily
 263       AMD_F15_OR_ALL                           // CpuRevision
 264     },
 265     {AMD_PF_MULTI_LINK},                      // platformFeatures
 266     {{
 267       PERFORMANCE_PROBEFILTER,
 268       (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // MCM1 or MCM2h
 269       PACKAGE_TYPE_MCM,
 270       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 271       0x00900300,                           // regData
 272       0x00F00300,                           // regMask
 273     }}
 274   },
 275 // F3x140 - SRI_to_XCS Token Count
 276 // bits[9:8] UpRspTok = 1
 277 // bits[23:20] FreeTok = 11
 278   {
 279     TokenPciRegister,
 280     {
 281       AMD_FAMILY_15,                        // CpuFamily
 282       AMD_F15_OR_ALL                           // CpuRevision
 283     },
 284     {AMD_PF_MULTI_LINK},  // platformFeatures
 285     {{
 286       PERFORMANCE_PROFILE_ALL,
 287       (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // MCM2
 288       PACKAGE_TYPE_MCM,
 289       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 290       0x00B00100,                             // regData
 291       0x00F00300,                           // regMask
 292     }}
 293   },
 294 // F3x140 - SRI_to_XCS Token Count
 295 // bits[9:8] UpRspTok = 3
 296 // bits[23:20] FreeTok = 10
 297   {
 298     TokenPciRegister,
 299     {
 300       AMD_FAMILY_15,                        // CpuFamily
 301       AMD_F15_OR_ALL                           // CpuRevision
 302     },
 303     {AMD_PF_MULTI_LINK},                      // platformFeatures
 304     {{
 305       PERFORMANCE_PROFILE_ALL,
 306       (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE),     // MCM4h
 307       PACKAGE_TYPE_MCM,
 308       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 309       0x00A00300,                           // regData
 310       0x00F00300,                           // regMask
 311     }}
 312   },
 313 // F3x140 - SRI_to_XCS Token Count
 314 // bits[9:8] UpRspTok = 1
 315 // bits[23:20] FreeTok = 9
 316   {
 317     TokenPciRegister,
 318     {
 319       AMD_FAMILY_15,                        // CpuFamily
 320       AMD_F15_OR_ALL                           // CpuRevision
 321     },
 322     {AMD_PF_MULTI_LINK},  // platformFeatures
 323     {{
 324       PERFORMANCE_PROFILE_ALL,
 325       (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // MCM4
 326       PACKAGE_TYPE_MCM,
 327       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
 328       0x00900100,                           // regData
 329       0x00F00300,                           // regMask
 330     }}
 331   },
 332 // F3x148 - Link to XCS Token Count
 333 // bits[1:0] ReqTok0 = 2
 334 // bits[3:2] PReqTok0 = 2
 335 // bits[5:4] RspTok0 = 2
 336 // bits[7:6] ProbeTok0 = 2
 337 // bits[9:8] IsocReqTok0 = 1
 338 // bits[11:10] IsocPreqTok0 = 0
 339 // bits[13:12] IsocRspTok0 = 0
 340 // bits[15:14] FreeTok[1:0] = 3
 341 // bits[17:16] ReqTok1 = 0
 342 // bits[19:18] PReqTok1 = 0
 343 // bits[21:20] RspTok1 = 0
 344 // bits[23:22] ProbeTok1= 0
 345 // bits[24] IsocReqTok1 = 0
 346 // bits[26] IsocPreqTok1 = 0
 347 // bits[28] IsocRspTok1 = 0
 348 // bits[31:30] FreeTok[3:2] = 0
 349   {
 350     HtTokenPciRegister,
 351     {
 352       AMD_FAMILY_15,                        // CpuFamily
 353       AMD_F15_OR_ALL                           // CpuRevision
 354     },
 355     {AMD_PF_MULTI_LINK},  // platformFeatures
 356     {{
 357       (COUNT_RANGE_ALL | COUNT_RANGE_NONE), // SCM
 358       PERFORMANCE_PROFILE_ALL,
 359       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
 360       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 361       0x0000C1AA,                           // regData
 362       0xD5FFFFFF,                           // regMask
 363     }}
 364   },
 365 // F3x148 - Link to XCS Token Count
 366 // bits[1:0] ReqTok0 = 2
 367 // bits[3:2] PReqTok0 = 2
 368 // bits[5:4] RspTok0 = 2
 369 // bits[7:6] ProbeTok0 = 2
 370 // bits[9:8] IsocReqTok0 = 1
 371 // bits[11:10] IsocPreqTok0 = 0
 372 // bits[13:12] IsocRspTok0 = 0
 373 // bits[15:14] FreeTok[1:0] = 0
 374 // bits[17:16] ReqTok1 = 0
 375 // bits[19:18] PReqTok1 = 0
 376 // bits[21:20] RspTok1 = 0
 377 // bits[23:22] ProbeTok1= 0
 378 // bits[24] IsocReqTok1 = 0
 379 // bits[26] IsocPreqTok1 = 0
 380 // bits[28] IsocRspTok1 = 0
 381 // bits[31:30] FreeTok[3:2] = 0
 382   {
 383     HtTokenPciRegister,
 384     {
 385       AMD_FAMILY_15,                        // CpuFamily
 386       AMD_F15_OR_ALL                           // CpuRevision
 387     },
 388     {AMD_PF_MULTI_LINK},  // platformFeatures
 389     {{
 390       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h.
 391       PERFORMANCE_PROFILE_ALL,
 392       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
 393       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 394       0x000001AA,                           // regData
 395       0xD5FFFFFF,                           // regMask
 396     }}
 397   },
 398 // F3x148 - Link to XCS Token Count
 399 // bits[1:0] ReqTok0 = 2
 400 // bits[3:2] PReqTok0 = 2
 401 // bits[5:4] RspTok0 = 2
 402 // bits[7:6] ProbeTok0 = 1
 403 // bits[9:8] IsocReqTok0 = 1
 404 // bits[11:10] IsocPreqTok0 = 0
 405 // bits[13:12] IsocRspTok0 = 0
 406 // bits[15:14] FreeTok[1:0] = 0
 407 // bits[17:16] ReqTok1 = 0
 408 // bits[19:18] PReqTok1 = 0
 409 // bits[21:20] RspTok1 = 0
 410 // bits[23:22] ProbeTok1= 0
 411 // bits[24] IsocReqTok1 = 0
 412 // bits[26] IsocPreqTok1 = 0
 413 // bits[28] IsocRspTok1 = 0
 414 // bits[31:30] FreeTok[3:2] = 0
 415   {
 416     HtTokenPciRegister,
 417     {
 418       AMD_FAMILY_15,                        // CpuFamily
 419       AMD_F15_OR_ALL                           // CpuRevision
 420     },
 421     {AMD_PF_MULTI_LINK},  // platformFeatures
 422     {{
 423       (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (2, 3)),  // MCM2 or MCM4h
 424       PERFORMANCE_PROFILE_ALL,
 425       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
 426       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 427       0x0000016A,                           // regData
 428       0xD5FFFFFF,                           // regMask
 429     }}
 430   },
 431 // F3x148 - Link to XCS Token Count
 432 // bits[1:0] ReqTok0 = 2
 433 // bits[3:2] PReqTok0 = 1
 434 // bits[5:4] RspTok0 = 1
 435 // bits[7:6] ProbeTok0 = 2
 436 // bits[9:8] IsocReqTok0 = 1
 437 // bits[11:10] IsocPreqTok0 = 0
 438 // bits[13:12] IsocRspTok0 = 0
 439 // bits[15:14] FreeTok[1:0] = 0
 440 // bits[17:16] ReqTok1 = 0
 441 // bits[19:18] PReqTok1 = 0
 442 // bits[21:20] RspTok1 = 0
 443 // bits[23:22] ProbeTok1= 0
 444 // bits[24] IsocReqTok1 = 0
 445 // bits[26] IsocPreqTok1 = 0
 446 // bits[28] IsocRspTok1 = 0
 447 // bits[31:30] FreeTok[3:2] = 0
 448   {
 449     HtTokenPciRegister,
 450     {
 451       AMD_FAMILY_15,                        // CpuFamily
 452       AMD_F15_OR_ALL                           // CpuRevision
 453     },
 454     {AMD_PF_MULTI_LINK},  // platformFeatures
 455     {{
 456       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // MCM4
 457       PERFORMANCE_PROFILE_ALL,
 458       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
 459       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 460       0x00000196,                           // regData
 461       0xD5FFFFFF,                           // regMask
 462     }}
 463   },
 464 // F3x148 - Link to XCS Token Count
 465 // bits[1:0] ReqTok0 = 1
 466 // bits[3:2] PReqTok0 = 1
 467 // bits[5:4] RspTok0 = 1
 468 // bits[7:6] ProbeTok0 = 1
 469 // bits[9:8] IsocReqTok0 = 1
 470 // bits[11:10] IsocPreqTok0 = 0
 471 // bits[13:12] IsocRspTok0 = 0
 472 // bits[15:14] FreeTok[1:0] = 0
 473 // bits[17:16] ReqTok1 = 1
 474 // bits[19:18] PReqTok1 = 1
 475 // bits[21:20] RspTok1 = 1
 476 // bits[23:22] ProbeTok1= 1
 477 // bits[24] IsocReqTok1 = 0
 478 // bits[26] IsocPreqTok1 = 0
 479 // bits[28] IsocRspTok1 = 0
 480 // bits[31:30] FreeTok[3:2] = 0
 481   {
 482     HtTokenPciRegister,
 483     {
 484       AMD_FAMILY_15,                        // CpuFamily
 485       AMD_F15_OR_ALL                           // CpuRevision
 486     },
 487     {AMD_PF_MULTI_LINK},  // platformFeatures
 488     {{
 489       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h.
 490       PERFORMANCE_PROFILE_ALL,
 491       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
 492       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 493       0x00550155,                           // regData
 494       0xD5FFFFFF,                           // regMask
 495     }}
 496   },
 497   // F3x148 - Link to XCS Token Count
 498 // bits[1:0] ReqTok0 = 1
 499 // bits[3:2] PReqTok0 = 1
 500 // bits[5:4] RspTok0 = 2
 501 // bits[7:6] ProbeTok0 = 1
 502 // bits[9:8] IsocReqTok0 = 1
 503 // bits[11:10] IsocPreqTok0 = 0
 504 // bits[13:12] IsocRspTok0 = 0
 505 // bits[15:14] FreeTok[1:0] = 0
 506 // bits[17:16] ReqTok1 = 1
 507 // bits[19:18] PReqTok1 = 1
 508 // bits[21:20] RspTok1 = 1
 509 // bits[23:22] ProbeTok1= 1
 510 // bits[24] IsocReqTok1 = 0
 511 // bits[26] IsocPreqTok1 = 0
 512 // bits[28] IsocRspTok1 = 0
 513 // bits[31:30] FreeTok[3:2] = 0
 514   {
 515     HtTokenPciRegister,
 516     {
 517       AMD_FAMILY_15,                        // CpuFamily
 518       AMD_F15_OR_ALL                           // CpuRevision
 519     },
 520     {AMD_PF_MULTI_LINK},  // platformFeatures
 521     {{
 522       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h.
 523       PERFORMANCE_PROBEFILTER,
 524       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
 525       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 526       0x00550165,                           // regData
 527       0xD5FFFFFF,                           // regMask
 528     }}
 529   },
 530 // F3x148 - Link to XCS Token Count
 531 // bits[1:0] ReqTok0 = 1
 532 // bits[3:2] PReqTok0 = 1
 533 // bits[5:4] RspTok0 = 1
 534 // bits[7:6] ProbeTok0 = 1
 535 // bits[9:8] IsocReqTok0 = 1
 536 // bits[11:10] IsocPreqTok0 = 0
 537 // bits[13:12] IsocRspTok0 = 0
 538 // bits[15:14] FreeTok[1:0] = 2
 539 // bits[17:16] ReqTok1 = 1
 540 // bits[19:18] PReqTok1 = 1
 541 // bits[21:20] RspTok1 = 1
 542 // bits[23:22] ProbeTok1= 1
 543 // bits[24] IsocReqTok1 = 1
 544 // bits[26] IsocPreqTok1 = 0
 545 // bits[28] IsocRspTok1 = 0
 546 // bits[31:30] FreeTok[3:2] = 0
 547   {
 548     HtTokenPciRegister,
 549     {
 550       AMD_FAMILY_15,                        // CpuFamily
 551       AMD_F15_OR_ALL                           // CpuRevision
 552     },
 553     {AMD_PF_MULTI_LINK},  // platformFeatures
 554     {{
 555       (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (3, 3)),     // MCM2
 556       PERFORMANCE_PROFILE_ALL,
 557       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
 558       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 559       0x01558155,                           // regData
 560       0xD5FFFFFF,                           // regMask
 561     }}
 562   },
 563 // F3x148 - Link to XCS Token Count
 564 // bits[1:0] ReqTok0 = 1
 565 // bits[3:2] PReqTok0 = 1
 566 // bits[5:4] RspTok0 = 1
 567 // bits[7:6] ProbeTok0 = 1
 568 // bits[9:8] IsocReqTok0 = 1
 569 // bits[11:10] IsocPreqTok0 = 0
 570 // bits[13:12] IsocRspTok0 = 0
 571 // bits[15:14] FreeTok[1:0] = 0
 572 // bits[17:16] ReqTok1 = 1
 573 // bits[19:18] PReqTok1 = 1
 574 // bits[21:20] RspTok1 = 1
 575 // bits[23:22] ProbeTok1= 1
 576 // bits[24] IsocReqTok1 = 1
 577 // bits[26] IsocPreqTok1 = 0
 578 // bits[28] IsocRspTok1 = 0
 579 // bits[31:30] FreeTok[3:2] = 1
 580   {
 581     HtTokenPciRegister,
 582     {
 583       AMD_FAMILY_15,                        // CpuFamily
 584       AMD_F15_OR_ALL                           // CpuRevision
 585     },
 586     {AMD_PF_MULTI_LINK},  // platformFeatures
 587     {{
 588       (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (2, 2)),     // MCM4h
 589       PERFORMANCE_PROFILE_ALL,
 590       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
 591       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 592       0x41550155,                           // regData
 593       0xD5FFFFFF,                           // regMask
 594     }}
 595   },
 596 // F3x148 - Link to XCS Token Count
 597 // bits[1:0] ReqTok0 = 1
 598 // bits[3:2] PReqTok0 = 1
 599 // bits[5:4] RspTok0 = 1
 600 // bits[7:6] ProbeTok0 = 1
 601 // bits[9:8] IsocReqTok0 = 1
 602 // bits[11:10] IsocPreqTok0 = 0
 603 // bits[13:12] IsocRspTok0 = 0
 604 // bits[15:14] FreeTok[1:0] = 0
 605 // bits[17:16] ReqTok1 = 1
 606 // bits[19:18] PReqTok1 = 1
 607 // bits[21:20] RspTok1 = 1
 608 // bits[23:22] ProbeTok1= 1
 609 // bits[24] IsocReqTok1 = 1
 610 // bits[26] IsocPreqTok1 = 0
 611 // bits[28] IsocRspTok1 = 0
 612 // bits[31:30] FreeTok[3:2] = 0
 613   {
 614     HtTokenPciRegister,
 615     {
 616       AMD_FAMILY_15,                        // CpuFamily
 617       AMD_F15_OR_ALL                           // CpuRevision
 618     },
 619     {AMD_PF_MULTI_LINK},  // platformFeatures
 620     {{
 621       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // MCM4
 622       PERFORMANCE_PROFILE_ALL,
 623       (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
 624       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 625       0x01550155,                           // regData
 626       0xD5FFFFFF,                           // regMask
 627     }}
 628   },
 629 // F3x148 - Link to XCS Token Count
 630 // bits[1:0] ReqTok0 = 2
 631 // bits[3:2] PReqTok0 = 2
 632 // bits[5:4] RspTok0 = 2
 633 // bits[7:6] ProbeTok0 = 0
 634 // bits[9:8] IsocReqTok0 = 1
 635 // bits[11:10] IsocPreqTok0 = 0
 636 // bits[13:12] IsocRspTok0 = 0
 637 // bits[15:14] FreeTok[1:0] = 3
 638 // bits[17:16] ReqTok1 = 0
 639 // bits[19:18] PReqTok1 = 0
 640 // bits[21:20] RspTok1 = 0
 641 // bits[23:22] ProbeTok1= 0
 642 // bits[24] IsocReqTok1 = 0
 643 // bits[26] IsocPreqTok1 = 0
 644 // bits[28] IsocRspTok1 = 0
 645 // bits[31:30] FreeTok[3:2] = 0
 646   {
 647     HtTokenPciRegister,
 648     {
 649       AMD_FAMILY_15,                      // CpuFamily
 650       AMD_F15_OR_ALL                         // CpuRevision
 651     },
 652     {AMD_PF_MULTI_LINK},  // platformFeatures
 653     {{
 654       (COUNT_RANGE_ALL | COUNT_RANGE_NONE),    //SCM
 655       PERFORMANCE_PROFILE_ALL,
 656       (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT  | HT_HOST_FEAT_GANGED),
 657       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 658       0x0000C12A,                           // regData
 659       0xD5FFFFFF,                           // regMask
 660     }}
 661   },
 662 // F3x148 - Link to XCS Token Count
 663 // bits[1:0] ReqTok0 = 2
 664 // bits[3:2] PReqTok0 = 2
 665 // bits[5:4] RspTok0 = 2
 666 // bits[7:6] ProbeTok0 = 0
 667 // bits[9:8] IsocReqTok0 = 1
 668 // bits[11:10] IsocPreqTok0 = 0
 669 // bits[13:12] IsocRspTok0 = 0
 670 // bits[15:14] FreeTok[1:0] = 0
 671 // bits[17:16] ReqTok1 = 0
 672 // bits[19:18] PReqTok1 = 0
 673 // bits[21:20] RspTok1 = 0
 674 // bits[23:22] ProbeTok1= 0
 675 // bits[24] IsocReqTok1 = 0
 676 // bits[26] IsocPreqTok1 = 0
 677 // bits[28] IsocRspTok1 = 0
 678 // bits[31:30] FreeTok[3:2] = 0
 679   {
 680     HtTokenPciRegister,
 681     {
 682       AMD_FAMILY_15,                      // CpuFamily
 683       AMD_F15_OR_ALL                         // CpuRevision
 684     },
 685     {AMD_PF_MULTI_LINK},  // platformFeatures
 686     {{
 687       (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE), // MCM1 or MCM2h or MCM2 or MCM4h
 688       PERFORMANCE_PROFILE_ALL,
 689       (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT  | HT_HOST_FEAT_GANGED),
 690       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 691       0x0000012A,                           // regData
 692       0xD5FFFFFF,                           // regMask
 693     }}
 694   },
 695 // F3x148 - Link to XCS Token Count
 696 // bits[1:0] ReqTok0 = 2
 697 // bits[3:2] PReqTok0 = 2
 698 // bits[5:4] RspTok0 = 2
 699 // bits[7:6] ProbeTok0 = 2
 700 // bits[9:8] IsocReqTok0 = 2
 701 // bits[11:10] IsocPreqTok0 = 0
 702 // bits[13:12] IsocRspTok0 = 0
 703 // bits[15:14] FreeTok[1:0] = 0
 704 // bits[17:16] ReqTok1 = 0
 705 // bits[19:18] PReqTok1 = 0
 706 // bits[21:20] RspTok1 = 0
 707 // bits[23:22] ProbeTok1= 0
 708 // bits[24] IsocReqTok1 = 0
 709 // bits[26] IsocPreqTok1 = 0
 710 // bits[28] IsocRspTok1 = 0
 711 // bits[31:30] FreeTok[3:2] = 0
 712   {
 713     HtTokenPciRegister,
 714     {
 715       AMD_FAMILY_15,                      // CpuFamily
 716       AMD_F15_OR_ALL                         // CpuRevision
 717     },
 718     {AMD_PF_MULTI_LINK},  // platformFeatures
 719     {{
 720       (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // MCM4
 721       PERFORMANCE_PROFILE_ALL,
 722       (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT  | HT_HOST_FEAT_GANGED),
 723       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
 724       0x000002AA,                           // regData
 725       0xD5FFFFFF,                           // regMask
 726     }}
 727   },
 728   // F3x158 - Link to XCS Token Count Registers
 729   // bits [3:0]LnkToXcsDRToken = 0
 730   {
 731     PciRegister,
 732     {
 733       AMD_FAMILY_15,                      // CpuFamily
 734       AMD_F15_OR_ALL                         // CpuRevision
 735     },
 736     {AMD_PF_MULTI_LINK},
 737     {{
 738       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
 739       0x00000000,
 740       0x0000000F
 741     }}
 742   },
 743 };
 744
 745 CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable = {
 746   PrimaryCores,
 747   (sizeof (F15OrMultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
 748   F15OrMultiLinkPciRegisters,
 749 };