src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_15 Orochi L3 dependent feature support functions.
   6  *
   7  * Provides the functions necessary to initialize L3 dependent features.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  CPU/Family/0x15/OR
  12  * @e \$Revision: 60552 $   @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $
  13  *
  14  */
  15 /*
  16  ******************************************************************************
  17  *
  18  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  ******************************************************************************
  44  */
  45
  46
  47 /*
  48  *----------------------------------------------------------------------------
  49  *                                MODULES USED
  50  *
  51  *----------------------------------------------------------------------------
  52  */
  53
  54 #include "AGESA.h"
  55 #include "amdlib.h"
  56 #include "Ids.h"
  57 #include "CommonReturns.h"
  58 #include "cpuRegisters.h"
  59 #include "cpuF15PowerMgmt.h"
  60 #include "cpuF15OrPowerMgmt.h"
  61 #include "cpuLateInit.h"
  62 #include "cpuServices.h"
  63 #include "GeneralServices.h"
  64 #include "cpuFamilyTranslation.h"
  65 #include "cpuL3Features.h"
  66 #include "Filecode.h"
  67 CODE_GROUP (G3_DXE)
  68 RDATA_GROUP (G3_DXE)
  69
  70 #define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE
  71
  72 /*----------------------------------------------------------------------------
  73  *                          DEFINITIONS AND MACROS
  74  *
  75  *----------------------------------------------------------------------------
  76  */
  77 #define L3Cache8_0M 0xCCCC
  78
  79 /*----------------------------------------------------------------------------
  80  *                           TYPEDEFS AND STRUCTURES
  81  *
  82  *----------------------------------------------------------------------------
  83  */
  84
  85 /**
  86  * The family 15h background scrubber context structure.
  87  *
  88  * These fields need to be saved, modified, then restored
  89  * per die as part of HT Assist initialization.
  90  */
  91 typedef struct {
  92   UINT32  DramScrub:5;               ///< DRAM scrub rate
  93   UINT32  :3;                        ///< Reserved
  94   UINT32  L3Scrub:5;                 ///< L3 scrub rate
  95   UINT32  :3;                        ///< Reserved
  96   UINT32  Redirect:1;                ///< DRAM scrubber redirect enable
  97   UINT32  :15;                       ///< Reserved
  98 } F15_SCRUB_CONTEXT;
  99
 100
 101 /*----------------------------------------------------------------------------
 102  *                        PROTOTYPES OF LOCAL FUNCTIONS
 103  *
 104  *----------------------------------------------------------------------------
 105  */
 106 BOOLEAN
 107 F15OrIsNonOptimalConfig (
 108   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 109   IN       UINT32 Socket,
 110   IN       AMD_CONFIG_PARAMS *StdHeader
 111   );
 112
 113 /*----------------------------------------------------------------------------
 114  *                            EXPORTED FUNCTIONS
 115  *
 116  *----------------------------------------------------------------------------
 117  */
 118
 119
 120 /*---------------------------------------------------------------------------------------*/
 121 /**
 122  *  Check to see if the input CPU supports L3 dependent features.
 123  *
 124  * @param[in]    L3FeatureServices   L3 feature family services.
 125  * @param[in]    Socket              Processor socket to check.
 126  * @param[in]    StdHeader           Config Handle for library, services.
 127  * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
 128  *
 129  * @retval       TRUE                L3 dependent features are supported.
 130  * @retval       FALSE               L3 dependent features are not supported.
 131  *
 132  */
 133 BOOLEAN
 134 STATIC
 135 F15OrIsL3FeatureSupported (
 136   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 137   IN       UINT32 Socket,
 138   IN       AMD_CONFIG_PARAMS *StdHeader,
 139   IN       PLATFORM_CONFIGURATION *PlatformConfig
 140   )
 141 {
 142   UINT32       Module;
 143   UINT32       LocalPciRegister;
 144   BOOLEAN      IsSupported;
 145   PCI_ADDR     PciAddress;
 146   AGESA_STATUS IgnoredStatus;
 147
 148   IsSupported = FALSE;
 149   for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
 150     if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
 151       PciAddress.Address.Function = FUNC_3;
 152       PciAddress.Address.Register = NB_CAPS_REG;
 153       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 154       if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) {
 155         IsSupported = TRUE;
 156       }
 157       break;
 158     }
 159   }
 160   return IsSupported;
 161 }
 162
 163
 164 /*---------------------------------------------------------------------------------------*/
 165 /**
 166  *  Enable the Probe filter feature
 167  *
 168  * @param[in]    L3FeatureServices   L3 family services.
 169  * @param[in]    Socket              Processor socket to check.
 170  * @param[in]    StdHeader           Config Handle for library, services.
 171  *
 172  */
 173 VOID
 174 STATIC
 175 F15OrHtAssistInit (
 176   IN       L3_FEATURE_FAMILY_SERVICES  *L3FeatureServices,
 177   IN       UINT32  Socket,
 178   IN       AMD_CONFIG_PARAMS      *StdHeader
 179   )
 180 {
 181   UINT32                     Module;
 182   UINT32                     L3CacheParamRegister;
 183   UINT32                     PfCtrlRegister;
 184   PCI_ADDR                   PciAddress;
 185   AGESA_STATUS               IgnoredStatus;
 186
 187   for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
 188     if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
 189       PciAddress.Address.Function = FUNC_3;
 190       PciAddress.Address.Register = L3_CACHE_PARAM_REG;
 191       LibAmdPciRead (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader);
 192       ((L3_CACHE_PARAM_REGISTER *) &L3CacheParamRegister)->L3TagInit = 1;
 193       LibAmdPciWrite (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader);
 194       do {
 195         LibAmdPciRead (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader);
 196       } while (((L3_CACHE_PARAM_REGISTER *) &L3CacheParamRegister)->L3TagInit != 0);
 197
 198       PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
 199       LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
 200       ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFWayHashEn = 1;
 201       ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFLoIndexHashEn = 1;
 202       ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFWayNum = 2;
 203       ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheEn = 0xF;
 204       if ((L3CacheParamRegister & 0xFFFF) == L3Cache8_0M) {
 205         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize0 = 1;
 206         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize1 = 1;
 207         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize2 = 1;
 208         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize3 = 1;
 209         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFMode = 3;
 210         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl = 2;
 211       } else {
 212         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize0 = 0;
 213         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize1 = 0;
 214         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize2 = 0;
 215         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize3 = 0;
 216         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFMode = 2;
 217         ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl = 0;
 218       }
 219       LibAmdPciWrite (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
 220
 221       do {
 222         LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
 223       } while (((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFInitDone != 1);
 224       IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
 225     }
 226   }
 227 }
 228
 229
 230 /*---------------------------------------------------------------------------------------*/
 231 /**
 232  *  Enable the ATM Mode feature.
 233  *
 234  * @param[in]    L3FeatureServices    L3 feature family services.
 235  * @param[in]    Socket               Processor socket to check.
 236  * @param[in]    StdHeader            Config Handle for library, services.
 237  *
 238  */
 239 VOID
 240 STATIC
 241 F15OrAtmModeInit (
 242   IN       L3_FEATURE_FAMILY_SERVICES  *L3FeatureServices,
 243   IN       UINT32  Socket,
 244   IN       AMD_CONFIG_PARAMS      *StdHeader
 245   )
 246 {
 247   UINT32                     Module;
 248   UINT32                     LocalPciRegister;
 249   PCI_ADDR                   PciAddress;
 250   AGESA_STATUS               IgnoredStatus;
 251
 252   for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
 253     if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
 254       PciAddress.Address.Function = FUNC_0;
 255       PciAddress.Address.Register = LTC_REG;
 256       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 257       ((LTC_REGISTER *) &LocalPciRegister)->ATMModeEn = 1;
 258       LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 259
 260       PciAddress.Address.Function = FUNC_3;
 261       PciAddress.Address.Register = L3_CONTROL_1_REG;
 262       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 263       ((L3_CONTROL_1_REGISTER *) &LocalPciRegister)->L3ATMModeEn = 1;
 264       LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 265     }
 266   }
 267 }
 268
 269
 270 /*---------------------------------------------------------------------------------------*/
 271 /**
 272  *  Save the current settings of the scrubbers, and disabled them.
 273  *
 274  * @param[in]    L3FeatureServices   L3 feature family services.
 275  * @param[in]    Socket              Processor socket to check.
 276  * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
 277  * @param[in]    StdHeader           Config Handle for library, services.
 278  *
 279  */
 280 VOID
 281 STATIC
 282 F15OrGetL3ScrubCtrl (
 283   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 284   IN       UINT32 Socket,
 285   IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
 286   IN       AMD_CONFIG_PARAMS *StdHeader
 287   )
 288 {
 289   UINT32       Module;
 290   UINT32       ScrubCtrl;
 291   UINT32       ScrubAddr;
 292   PCI_ADDR     PciAddress;
 293   AGESA_STATUS IgnoredStatus;
 294
 295   for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
 296     if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
 297
 298       ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
 299
 300       PciAddress.Address.Function = FUNC_3;
 301       PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
 302       LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
 303
 304       PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
 305       LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
 306
 307       ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
 308         ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
 309       ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
 310         ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
 311       ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
 312         ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
 313
 314       ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
 315       ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
 316       ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
 317       LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
 318       PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
 319       LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
 320     }
 321   }
 322 }
 323
 324
 325 /*---------------------------------------------------------------------------------------*/
 326 /**
 327  *  Restore the initial settings for the scrubbers.
 328  *
 329  * @param[in]    L3FeatureServices   L3 Feature family services.
 330  * @param[in]    Socket              Processor socket to check.
 331  * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
 332  * @param[in]    StdHeader           Config Handle for library, services.
 333  *
 334  */
 335 VOID
 336 STATIC
 337 F15OrSetL3ScrubCtrl (
 338   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 339   IN       UINT32 Socket,
 340   IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
 341   IN       AMD_CONFIG_PARAMS *StdHeader
 342   )
 343 {
 344   UINT32       Module;
 345   UINT32       LocalPciRegister;
 346   PCI_ADDR     PciAddress;
 347   AGESA_STATUS IgnoredStatus;
 348
 349   for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
 350     if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
 351
 352       ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
 353
 354       PciAddress.Address.Function = FUNC_3;
 355       PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
 356       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 357       ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub =
 358         ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
 359       ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub =
 360         ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
 361       LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 362
 363       PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
 364       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 365       ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn =
 366         ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
 367       LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 368     }
 369   }
 370 }
 371
 372
 373 /*---------------------------------------------------------------------------------------*/
 374 /**
 375  *  Set MSR bits required for L3 feature support on each core.
 376  *
 377  * @param[in]    L3FeatureServices    L3 Feature family services.
 378  * @param[in]    HtAssistEnabled      Indicates whether Ht Assist is enabled.
 379  * @param[in]    StdHeader            Config Handle for library, services.
 380  *
 381  */
 382 VOID
 383 STATIC
 384 F15OrHookDisableCache (
 385   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 386   IN       BOOLEAN HtAssistEnabled,
 387   IN       AMD_CONFIG_PARAMS *StdHeader
 388   )
 389 {
 390   UINT64  LocalMsrRegister;
 391
 392   // This bit is set only if Probe Filter is enabled.
 393   if (HtAssistEnabled) {
 394     LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
 395     LocalMsrRegister |= BIT42;
 396     LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
 397   }
 398 }
 399
 400
 401 /*---------------------------------------------------------------------------------------*/
 402 /**
 403  *  Check to see if the input CPU is running in the optimal configuration.
 404  *
 405  * @param[in]    L3FeatureServices   L3 Feature family services.
 406  * @param[in]    Socket              Processor socket to check.
 407  * @param[in]    StdHeader           Config Handle for library, services.
 408  *
 409  * @retval       TRUE               HT Assist is running sub-optimally.
 410  * @retval       FALSE              HT Assist is running optimally.
 411  *
 412  */
 413 BOOLEAN
 414 F15OrIsNonOptimalConfig (
 415   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 416   IN       UINT32 Socket,
 417   IN       AMD_CONFIG_PARAMS *StdHeader
 418   )
 419 {
 420   BOOLEAN      IsNonOptimal;
 421   BOOLEAN      IsMemoryPresent;
 422   UINT32       Module;
 423   UINT32       LocalPciRegister;
 424   PCI_ADDR     PciAddress;
 425   AGESA_STATUS IgnoredStatus;
 426
 427   IsNonOptimal = FALSE;
 428   for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
 429     if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
 430       IsMemoryPresent = FALSE;
 431       PciAddress.Address.Function = FUNC_2;
 432       PciAddress.Address.Register = DRAM_CFG_HI_REG0;
 433
 434       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 435       if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
 436         IsMemoryPresent = TRUE;
 437         if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 0x0a) {
 438           IsNonOptimal = TRUE;
 439           break;
 440         }
 441       }
 442
 443       PciAddress.Address.Register = DRAM_CFG_HI_REG1;
 444
 445       LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
 446       if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
 447         IsMemoryPresent = TRUE;
 448         if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 0x0a) {
 449           IsNonOptimal = TRUE;
 450           break;
 451         }
 452       }
 453       if (!IsMemoryPresent) {
 454         IsNonOptimal = TRUE;
 455         break;
 456       }
 457     }
 458   }
 459   return IsNonOptimal;
 460 }
 461
 462 /*---------------------------------------------------------------------------------------*/
 463 /**
 464  *  Check to see if the input CPU supports HT Assist.
 465  *
 466  * @param[in]    L3FeatureServices   L3 Feature family services.
 467  * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
 468  * @param[in]    StdHeader           Config Handle for library, services.
 469  *
 470  * @retval       TRUE               HT Assist is supported.
 471  * @retval       FALSE              HT Assist cannot be enabled.
 472  *
 473  */
 474 BOOLEAN
 475 STATIC
 476 F15OrIsHtAssistSupported (
 477   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 478   IN       PLATFORM_CONFIGURATION *PlatformConfig,
 479   IN       AMD_CONFIG_PARAMS *StdHeader
 480   )
 481 {
 482   BOOLEAN          IsSupported;
 483   UINT32           CpuCount;
 484   AP_MAILBOXES     ApMailboxes;
 485
 486   IsSupported = FALSE;
 487
 488   if (PlatformConfig->PlatformProfile.UseHtAssist) {
 489     CpuCount = GetNumberOfProcessors (StdHeader);
 490     ASSERT (CpuCount != 0);
 491
 492     if (CpuCount == 1) {
 493       GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
 494       if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
 495         IsSupported = TRUE;
 496       }
 497     } else if (CpuCount > 1) {
 498       IsSupported = TRUE;
 499     }
 500   }
 501   return IsSupported;
 502 }
 503
 504 /*---------------------------------------------------------------------------------------*/
 505 /**
 506  *  Check to see if the input CPU supports ATM Mode.
 507  *
 508  * @param[in]    L3FeatureServices   L3 Feature family services.
 509  * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
 510  * @param[in]    StdHeader           Config Handle for library, services.
 511  *
 512  * @retval       TRUE                ATM Mode is supported.
 513  * @retval       FALSE               ATM Mode cannot be enabled.
 514  *
 515  */
 516 BOOLEAN
 517 STATIC
 518 F15OrIsAtmModeSupported (
 519   IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
 520   IN       PLATFORM_CONFIGURATION *PlatformConfig,
 521   IN       AMD_CONFIG_PARAMS *StdHeader
 522   )
 523 {
 524   BOOLEAN IsSupported;
 525
 526   IsSupported = TRUE;
 527
 528   if (!PlatformConfig->PlatformProfile.UseAtmMode) {
 529     IsSupported = FALSE;
 530   }
 531   return IsSupported;
 532 }
 533
 534 CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features =
 535 {
 536   0,
 537   F15OrIsL3FeatureSupported,
 538   F15OrGetL3ScrubCtrl,
 539   F15OrSetL3ScrubCtrl,
 540   (PF_L3_FEATURE_BEFORE_INIT) CommonVoid,
 541   (PF_L3_FEATURE_AFTER_INIT) CommonVoid,
 542   F15OrHookDisableCache,
 543   (PF_L3_FEATURE_ENABLE_CACHE) CommonVoid,
 544   F15OrIsHtAssistSupported,
 545   F15OrHtAssistInit,
 546   F15OrIsNonOptimalConfig,
 547   F15OrIsAtmModeSupported,
 548   F15OrAtmModeInit,
 549 };