5 * AMD Family_10 P-State power check
7 * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
8 * described in the BKDG.
10 * @xrefitem bom "File Content Label" "Release Content"
12 * @e sub-project: CPU/F10
13 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
17 ******************************************************************************
19 * Copyright (C) 2012 Advanced Micro Devices, Inc.
20 * All rights reserved.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 * * Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * * Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
30 * its contributors may be used to endorse or promote products derived
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33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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37 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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42 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 ******************************************************************************
47 /*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
53 #include "cpuF10PowerMgmt.h"
54 #include "cpuRegisters.h"
55 #include "cpuApicUtilities.h"
56 #include "cpuFamilyTranslation.h"
57 #include "cpuF10PowerCheck.h"
58 #include "cpuServices.h"
59 #include "GeneralServices.h"
60 #include "cpuF10Utilities.h"
61 #include "OptionMultiSocket.h"
66 #define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE
68 /*----------------------------------------------------------------------------------------
69 * D E F I N I T I O N S A N D M A C R O S
70 *----------------------------------------------------------------------------------------
73 /*----------------------------------------------------------------------------------------
74 * T Y P E D E F S A N D S T R U C T U R E S
75 *----------------------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------------------
79 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
80 *----------------------------------------------------------------------------------------
86 IN AMD_CONFIG_PARAMS *StdHeader
91 F10PmPwrChkCopyPstate (
94 IN AMD_CONFIG_PARAMS *StdHeader
97 /*----------------------------------------------------------------------------------------
98 * E X P O R T E D F U N C T I O N S
99 *----------------------------------------------------------------------------------------
101 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
102 /*---------------------------------------------------------------------------------------*/
104 * Family 10h core 0 entry point for performing the family 10h Processor-
105 * Systemboard Power Delivery Check.
107 * The steps are as follows:
108 * 1. Starting with P0, loop through all P-states until a passing state is
109 * found. A passing state is one in which the current required by the
110 * CPU is less than the maximum amount of current that the system can
111 * provide to the CPU. If P0 is under the limit, no further action is
113 * 2. If at least one P-State is under the limit & at least one P-State is
114 * over the limit, the BIOS must:
115 * a. If the processor's current P-State is disabled by the power check,
116 * then the BIOS must request a transition to an enabled P-state
117 * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
118 * to reflect the new value.
119 * b. Copy the contents of the enabled P-state MSRs to the highest
120 * performance P-state locations.
121 * c. Request a P-state transition to the P-state MSR containing the
122 * COF/VID values currently applied.
123 * d. On revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then
124 * program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering.
125 * e. Adjust the following P-state parameters affected by the P-state
126 * MSR copy by subtracting the number of P-states that are disabled
127 * by the power check.
128 * 1. F3x64[HtcPstateLimit]
129 * 2. F3x68[StcPstateLimit]
130 * 3. F3xDC[PstateMaxVal]
131 * 3. If all P-States are over the limit, the BIOS must:
132 * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
133 * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
134 * MSRC001_0063[CurPstate] to reflect the new value.
135 * b. If F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
136 * MSR pointed to by F3xDC[PstateMaxVal] to MSRC001_0064 and set
137 * MSRC001_0064[PstateEn]
138 * c. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
139 * [CurPstate] to reflect the new value.
140 * d. Adjust the following P-state parameters to zero on revision D and earlier processors.
141 * On revision E processors adjust the following fields to F4x15C[NumBoostStates]:
142 * 1. F3x64[HtcPstateLimit]
143 * 2. F3x68[StcPstateLimit]
144 * 3. F3xDC[PstateMaxVal]
145 * e. For revision E systems with CPUID Fn8000_0007[CPB]=1, program F4x15C[BoostSrc]=0.
147 * @param[in] FamilySpecificServices The current Family Specific Services.
148 * @param[in] CpuEarlyParams Service parameters
149 * @param[in] StdHeader Config handle for library and services.
154 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
155 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
156 IN AMD_CONFIG_PARAMS *StdHeader
163 UINT32 LocalPciRegister;
171 UINT64 LocalMsrRegister;
173 AGESA_STATUS IgnoredSts;
174 PWRCHK_ERROR_DATA ErrorData;
176 // get the socket number
177 IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
178 ErrorData.SocketNumber = (UINT8)Socket;
182 // get the Max P-state value
183 for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
184 LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
185 if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
190 ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
193 for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
194 if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
195 if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
196 // Add to event log the Pstate that exceeded the current limit
197 PutEventLog (AGESA_WARNING,
198 CPU_EVENT_PM_PSTATE_OVERCURRENT,
199 Socket, Pstate, 0, 0, StdHeader);
207 // If all P-state registers are disabled, move P[PsMaxVal] to P0
208 // and transition to P0, then wait for CurPstate = 0
210 ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
212 // We only need to log this event on the BSC
213 if (ErrorData.AllowablePstateNumber == 0) {
214 PutEventLog (AGESA_FATAL,
215 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
216 Socket, 0, 0, 0, StdHeader);
220 GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
221 // Check if CPB is supported. if yes, get the number of boost states.
222 ErrorData.NumberofBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
224 TaskPtr.FuncAddress.PfApTaskI = F10PmPwrCheckCore;
225 TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
226 TaskPtr.DataTransfer.DataPtr = &ErrorData;
227 TaskPtr.DataTransfer.DataTransferFlags = 0;
228 TaskPtr.ExeFlags = WAIT_FOR_CORE;
229 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
232 // For revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then
233 // program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering.
234 if (ErrorData.NumberofBoostStates == 1) {
235 PciAddress.Address.Function = FUNC_4;
236 PciAddress.Address.Register = CPB_CTRL_REG;
237 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
238 ((CPB_CTRL_REGISTER *) &LocalPciRegister)->BoostSrc = 0;
239 LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
242 // F3x64[HtPstatelimit] -= disPsNum
243 // F3x68[StcPstateLimit]-= disPsNum
244 // F3xDC[PstateMaxVal]-= disPsNum
246 PciAddress.Address.Function = FUNC_3;
247 PciAddress.Address.Register = HTC_REG;
248 AndMask = 0xFFFFFFFF;
249 ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
251 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
252 PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
253 if (ErrorData.AllowablePstateNumber != 0) {
254 if (PstateLimit > DisPsNum) {
255 PstateLimit -= DisPsNum;
256 ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
259 ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = ErrorData.NumberofBoostStates;
261 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3x64
263 PciAddress.Address.Register = STC_REG;
264 AndMask = 0xFFFFFFFF;
265 ((STC_REGISTER *) &AndMask)->StcPstateLimit = 0;
267 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
268 PstateLimit = ((STC_REGISTER *) &LocalPciRegister)->StcPstateLimit;
269 if (ErrorData.AllowablePstateNumber != 0) {
270 if (PstateLimit > DisPsNum) {
271 PstateLimit -= DisPsNum;
272 ((STC_REGISTER *) &OrMask)->StcPstateLimit = PstateLimit;
275 ((STC_REGISTER *) &OrMask)->StcPstateLimit = ErrorData.NumberofBoostStates;
277 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3x68
279 PciAddress.Address.Register = CPTC2_REG;
280 AndMask = 0xFFFFFFFF;
281 ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
283 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
284 PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
285 if (ErrorData.AllowablePstateNumber != 0) {
286 if (PstateLimit > DisPsNum) {
287 PstateLimit -= DisPsNum;
288 ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
291 ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = ErrorData.NumberofBoostStates;
293 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3xDC
295 // Now that P0 has changed, recalculate VSSlamTime
296 F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
301 /*---------------------------------------------------------------------------------------*/
303 * Core-level error handler called if any p-states were determined to be out
304 * of range for the mother board.
306 * This function implements steps 2a-c and 3a-c on each core.
308 * @param[in] ErrorData Details about the error condition.
309 * @param[in] StdHeader Config handle for library and services.
316 IN AMD_CONFIG_PARAMS *StdHeader
324 UINT64 LocalMsrRegister;
325 CPU_SPECIFIC_SERVICES *FamilySpecificServices;
327 GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
328 PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
329 DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
330 ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
331 EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates;
333 LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
334 CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
336 if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
339 // Transition to Pstate Max if not there already
341 if ((CurrentPs + EnBsNum) != PsMaxVal) {
342 FamilySpecificServices->TransitionPstate (FamilySpecificServices, (PsMaxVal - EnBsNum), (BOOLEAN) TRUE, StdHeader);
347 // If Pstate Max is not 000b, copy Pstate max contents to P0 and switch
348 // to P0. This step uses software P-state numbering
351 F10PmPwrChkCopyPstate (EnBsNum, PsMaxVal, StdHeader);
352 FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
356 // move remaining P-state register(s) up
358 // Transition to a valid Pstate if current Pstate has been disabled
360 if ((CurrentPs + EnBsNum) < DisPsNum) {
361 FamilySpecificServices->TransitionPstate (FamilySpecificServices, (DisPsNum - EnBsNum), (BOOLEAN) TRUE, StdHeader);
362 CurrentPs = DisPsNum - EnBsNum;
366 // Move enabled Pstates up and disable the remainder. This step uses software P-state numbering.
367 if (DisPsNum > EnBsNum) {
368 for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
369 F10PmPwrChkCopyPstate ((i + EnBsNum), (i + DisPsNum), StdHeader);
373 // Transition to current COF/VID at shifted location
375 CurrentPs = ((CurrentPs + EnBsNum) - DisPsNum);
376 FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
378 i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
382 while (i <= PsMaxVal) {
383 FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
389 /*---------------------------------------------------------------------------------------*/
391 * Copies the contents of one P-State MSR to another.
393 * @param[in] Dest Destination p-state number
394 * @param[in] Src Source p-state number
395 * @param[in] StdHeader Config handle for library and services
400 F10PmPwrChkCopyPstate (
403 IN AMD_CONFIG_PARAMS *StdHeader
406 UINT64 LocalMsrRegister;
408 LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
409 LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);