src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10PciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 DR PCI tables with values as defined in BKDG
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/FAMILY/0x10
  10  * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "Ids.h"
  50 #include "cpuRegisters.h"
  51 #include "Table.h"
  52 #include "Filecode.h"
  53 CODE_GROUP (G1_PEICC)
  54 RDATA_GROUP (G2_PEI)
  55
  56 #define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE
  57
  58 /*----------------------------------------------------------------------------------------
  59  *                   D E F I N I T I O N S    A N D    M A C R O S
  60  *----------------------------------------------------------------------------------------
  61  */
  62
  63 /*----------------------------------------------------------------------------------------
  64  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  65  *----------------------------------------------------------------------------------------
  66  */
  67
  68 /*----------------------------------------------------------------------------------------
  69  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  70  *----------------------------------------------------------------------------------------
  71  */
  72
  73 /*----------------------------------------------------------------------------------------
  74  *                          E X P O R T E D    F U N C T I O N S
  75  *----------------------------------------------------------------------------------------
  76  */
  77
  78 //  P C I    T a b l e s
  79 // ----------------------
  80
  81 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PciRegisters[] =
  82 {
  83 // Function 0 - HT Config
  84
  85 // F0x68 - Link Transaction Control
  86 // bit[11]   , RespPassPW = 1
  87 // bit[19:17], for 8bit APIC config
  88 // bit[22:21], DsNpReqLmt = 10h
  89   {
  90     PciRegister,
  91     {
  92       AMD_FAMILY_10,                      // CpuFamily
  93       AMD_F10_ALL                         // CpuRevision
  94     },
  95     {AMD_PF_ALL},                           // platformFeatures
  96     {{
  97       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
  98       0x004E0800,                           // regData
  99       0x006E0800,                           // regMask
 100     }}
 101   },
 102 // F0x68 - Link Transaction Control
 103 // For uni-processor systems (that is, single link package processors), single core, and no L3:
 104 // [10, DisFillP] = 1b
 105 // [3, DisWrDwP] = 1b
 106 // [2, DisWrBP] = 1b
 107 // [1, DisRdDwP] = 1b
 108 // [0, DisRdBP] = 1b
 109   {
 110     ProfileFixup,
 111     {
 112       AMD_FAMILY_10,                        // CpuFamily
 113       AMD_F10_ALL                           // CpuRevision
 114     },
 115     { (AMD_PF_AND | AMD_PF_SINGLE_CORE | AMD_PF_SINGLE_LINK) },   // platformFeatures
 116     {{
 117       PERFORMANCE_NO_L3_CACHE,
 118       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
 119       0x0000040F,                           // regData
 120       0x0000040F,                           // regMask
 121     }}
 122   },
 123 // F0x[E4,C4,A4,84] - Link 0 Control Register
 124 // bit[13] LdtStopTriEn = 1
 125   {
 126     HtHostPciRegister,
 127     {
 128       AMD_FAMILY_10,                      // CpuFamily
 129       AMD_F10_ALL                         // CpuRevision
 130     },
 131     {AMD_PF_ALL},                           // platformFeatures
 132     {{
 133       HT_HOST_FEATURES_ALL,                 // link feats
 134       0x04,                                 // Address
 135       0x00002000,                           // regData
 136       0x00002000,                           // regMask
 137     }}
 138   },
 139 // F0x[E4,C4,A4,84] - Link 0 Control Register
 140 // bit [12] IsocEn = 0 default
 141   {
 142     HtHostPciRegister,
 143     {
 144       AMD_FAMILY_10,                      // CpuFamily
 145       AMD_F10_ALL                         // CpuRevision
 146     },
 147     { (AMD_PF_NFCM | AMD_PF_UMA) },
 148     {{
 149       HT_HOST_FEATURES_ALL,                 // link feats
 150       0x04,                                 // Address
 151       0x00000000,                           // regData
 152       0x00001000,                           // regMask
 153     }}
 154   },
 155 // F0x[E4,C4,A4,84] - Link 0 Control Register
 156 // bit [12] IsocEn = 1 for Isochronous control flow modes.
 157   {
 158     HtHostPciRegister,
 159     {
 160       AMD_FAMILY_10,                      // CpuFamily
 161       AMD_F10_ALL                         // CpuRevision
 162     },
 163     { (AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU) },
 164     {{
 165       HT_HOST_FEATURES_ALL,                 // link feats
 166       0x04,                                 // Address
 167       0x00001000,                           // regData
 168       0x00001000,                           // regMask
 169     }}
 170   },
 171 // F0x[F0,D0,B0,90] - Link Base Channel Buffer Count
 172 // bit[31] LockBc = 1
 173   {
 174     HtHostPciRegister,
 175     {
 176       AMD_FAMILY_10,                      // CpuFamily
 177       AMD_F10_ALL                         // CpuRevision
 178     },
 179     {AMD_PF_ALL},                           // platformFeatures
 180     {{
 181       HT_HOST_FEATURES_ALL,                 // link feats
 182       0x10,                                 // Address
 183       0x80000000,                           // regData
 184       0x80000000,                           // regMask
 185     }}
 186   },
 187 // F0x150 - Link Global Retry Control Register
 188 // bit[18:16] TotalRetryAttempts = 7
 189 // bit[13] HtRetryCrcDatInsDynEn = 1
 190 // bit[12]HtRetryCrcCmdPackDynEn = 1
 191 // bit[11:9] HtRetryCrcDatIns = 4
 192 // bit[8] HtRetryCrcCmdPack = 1
 193   {
 194     PciRegister,
 195     {
 196       AMD_FAMILY_10,                      // CpuFamily
 197       AMD_F10_ALL                         // CpuRevision
 198     },
 199     {AMD_PF_ALL},                           // platformFeatures
 200     {{
 201       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
 202       0x00073900,                           // regData
 203       0x00073F00,                           // regMask
 204     }}
 205   },
 206 // F0x16C - Link Global Extended Control Register
 207 // bit[15:13] ForceFullT0 = 0
 208 // bit[5:0] T0Time = 0x14
 209   {
 210     PciRegister,
 211     {
 212       AMD_FAMILY_10,                      // CpuFamily
 213       AMD_F10_ALL                         // CpuRevision
 214     },
 215     {AMD_PF_ALL},                           // platformFeatures
 216     {{
 217       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
 218       0x00000014,                           // regData
 219       0x0000E03F,                           // regMask
 220     }}
 221   },
 222 // F0x16C - Link Global Extended Control Register
 223 // bit[15:13] ForceFullT0 = 6
 224 // bit[5:0] T0Time = 0x26
 225   {
 226     PciRegister,
 227     {
 228       AMD_FAMILY_10,                      // CpuFamily
 229       AMD_F10_ALL                         // CpuRevision
 230     },
 231     {AMD_PF_SINGLE_LINK},                   // platformFeatures
 232     {{
 233       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
 234       0x0000C026,                           // regData
 235       0x0000E03F,                           // regMask
 236     }}
 237   },
 238 // F0x16C - Link Global Extended Control Register
 239 // bit[22:17] FullT0Time = 0x33
 240   {
 241     PciRegister,
 242     {
 243       AMD_FAMILY_10,                      // CpuFamily
 244       AMD_F10_C3                          // CpuRevision
 245     },
 246     {AMD_PF_ALL},                             // platformFeatures
 247     {{
 248       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
 249       0x00660000,                           // regData
 250       0x007E0000,                           // regMask
 251     }}
 252   },
 253
 254 // Function 1 - Map Init
 255
 256 // Before reading F1x114_x2 or F1x114_x3 software must initialize
 257 // the registers or NB Array MCA errors may occur.  BIOS should
 258 // initialize index 0h of F1x114_x2 and F1x114_x3 to prevent reads
 259 // from F1x114 from generating NB Array MCA errors.
 260 // BKDG Doc #3116 Rev 1.07
 261
 262 // F1x110 - Extended Address Map
 263   {
 264     PciRegister,
 265     {
 266       AMD_FAMILY_10,                      // CpuFamily
 267       AMD_F10_ALL                         // CpuRevision
 268     },
 269     {AMD_PF_ALL},                           // platformFeatures
 270     {{
 271       MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
 272       0x20000000,                           // regData
 273       0xFFFFFFFF,                           // regMask
 274     }}
 275   },
 276 // F1x114 - Extended Address Map
 277   {
 278     PciRegister,
 279     {
 280       AMD_FAMILY_10,                      // CpuFamily
 281       AMD_F10_ALL                         // CpuRevision
 282     },
 283     {AMD_PF_ALL},                           // platformFeatures
 284     {{
 285       MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
 286       0x00000000,                           // regData
 287       0xFFFFFFFF,                           // regMask
 288     }}
 289   },
 290 // F1x110 - Extended Address Map
 291   {
 292     PciRegister,
 293     {
 294       AMD_FAMILY_10,                      // CpuFamily
 295       AMD_F10_ALL                         // CpuRevision
 296     },
 297     {AMD_PF_ALL},                           // platformFeatures
 298     {{
 299       MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
 300       0x30000000,                           // regData
 301       0xFFFFFFFF,                           // regMask
 302     }}
 303   },
 304 // F1x114 - Extended Address Map
 305   {
 306     PciRegister,
 307     {
 308       AMD_FAMILY_10,                      // CpuFamily
 309       AMD_F10_ALL                         // CpuRevision
 310     },
 311     {AMD_PF_ALL},                           // platformFeatures
 312     {{
 313       MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
 314       0x00000000,                           // regData
 315       0xFFFFFFFF,                           // regMask
 316     }}
 317   },
 318
 319 // F2x1B0 - Extended Memory Controller Configuration Low
 320 // bits[10:8], CohPrefPrbLmt = 1
 321   {
 322     PciRegister,
 323     {
 324       AMD_FAMILY_10,                      // CpuFamily
 325       AMD_F10_ALL                         // CpuRevision
 326     },
 327     {AMD_PF_ALL},                           // platformFeatures
 328     {{
 329       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0),  // Address
 330       0x00000100,                           // regData
 331       0x00000700,                           // regMask
 332     }}
 333   },
 334
 335 // Function 3 - Misc. Control
 336 // F3x40 - MCA NB Control
 337 //
 338 // bit[8], MstrAbrtEn = 1
 339   {
 340     PciRegister,
 341     {
 342       AMD_FAMILY_10,                      // CpuFamily
 343       AMD_F10_ALL                         // CpuRevision
 344     },
 345     {AMD_PF_ALL},                           // platformFeatures
 346     {{
 347       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40),  // Address
 348       0x00000100,                           // regData
 349       0x00000100,                           // regMask
 350     }}
 351   },
 352 // F3x44 - MCA NB Configuration
 353 // bit[30]  SyncOnDramAdrParErrEn = 1
 354 // bit[27]  NB MCA to CPU0 Enable = 1
 355 // bit[25]  DisPciCfgCpuErrRsp = 1
 356 // bit[21]  SyncOnErr = 1
 357 // bit[20]  SyncOnWDTEn = 1
 358 // bit[6]   CpuErrDis = 1
 359 // bit[4]   SyncPktPropDis = 1
 360 // bit[3]   SyncPktGenDis = 1
 361 // bit[2]   SyncOnUcEccEn = 1
 362   {
 363     PciRegister,
 364     {
 365       AMD_FAMILY_10,                      // CpuFamily
 366       AMD_F10_ALL                         // CpuRevision
 367     },
 368     {AMD_PF_ALL},                           // platformFeatures
 369     {{
 370       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
 371       0x4A30005C,                           // regData
 372       0x4A30005C,                           // regMask
 373     }}
 374   },
 375 // F3x80 - ACPI Power State Control
 376 // ACPI FIDVID Change
 377 // bits[0] CpuPrbEn = 0
 378 // bits[1] NbLowPwrEn = 0
 379 // bits[2] NbGateEn = 0
 380 // bits[3] NbCofChg = 0
 381 // bits[4] AltVidEn = 0
 382 // bits[7:5] ClkDivisor = 0
 383 // ACPI State S1
 384 // bits[0] CpuPrbEn = 0
 385 // bits[1] NbLowPwrEn = 1
 386 // bits[2] NbGateEn = 1
 387 // bits[3] NbCofChg = 0
 388 // bits[4] AltVidEn = 0
 389 // bits[7:5] ClkDivisor = 7
 390   {
 391     PciRegister,
 392     {
 393       AMD_FAMILY_10,                      // CpuFamily
 394       AMD_F10_ALL                         // CpuRevision
 395     },
 396     {AMD_PF_ALL},                           // platformFeatures
 397     {{
 398       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 399       0xE6000000,                           // regData
 400       0xFFFF0000,                           // regMask
 401     }}
 402   },
 403 // F3x80 - ACPI Power State Control
 404 // ACPI FIDVID Change
 405 // bits[0] CpuPrbEn = 1
 406 // bits[1] NbLowPwrEn = 1
 407 // bits[2] NbGateEn = 0
 408 // bits[3] NbCofChg = 1
 409 // bits[4] AltVidEn = 0
 410 // bits[7:5] ClkDivisor = 0
 411   {
 412     PciRegister,
 413     {
 414       AMD_FAMILY_10,                      // CpuFamily
 415       AMD_F10_C3                          // CpuRevision
 416     },
 417     {AMD_PF_ALL},                           // platformFeatures
 418     {{
 419       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 420       0x000B0000,                           // regData
 421       0x00FF0000,                           // regMask
 422     }}
 423   },
 424 // F3x84 - ACPI Power State Control
 425 // ACPI State S3
 426 // bits[0] CpuPrbEn = 0
 427 // bits[1] NbLowPwrEn = 1
 428 // bits[2] NbGateEn = 1
 429 // bits[3] NbCofChg = 0
 430 // bits[4] AltVidEn = 0
 431 // bits[7:5] ClkDivisor = 7
 432 // ACPI State Throttling
 433 // bits[0] CpuPrbEn = 1
 434 // bits[1] NbLowPwrEn = 0
 435 // bits[2] NbGateEn = 0
 436 // bits[3] NbCofChg = 0
 437 // bits[4] AltVidEn = 0
 438 // bits[7:5] ClkDivisor = 2
 439 // ACPI State S4/S5
 440 // bits[0] CpuPrbEn = 0
 441 // bits[1] NbLowPwrEn = 1
 442 // bits[2] NbGateEn = 1
 443 // bits[3] NbCofChg = 0
 444 // bits[4] AltVidEn = 0
 445 // bits[7:5] ClkDivisor = 7
 446 // ACPI State C1
 447 // bits[0] CpuPrbEn = 0
 448 // bits[1] NbLowPwrEn = 0
 449 // bits[2] NbGateEn = 0
 450 // bits[3] NbCofChg = 0
 451 // bits[4] AltVidEn = 0
 452 // bits[7:5] ClkDivisor = 5
 453   {
 454     PciRegister,
 455     {
 456       AMD_FAMILY_10,                      // CpuFamily
 457       AMD_F10_ALL                         // CpuRevision
 458     },
 459     {AMD_PF_ALL},                           // platformFeatures
 460     {{
 461       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
 462       0x01E641E6,                           // regData
 463       0xFFFFFFFF,                           // regMask
 464     }}
 465   },
 466 // F3x84 - ACPI Power State Control
 467 // ACPI State C1
 468 // bits[0] CpuPrbEn = 0
 469 // bits[1] NbLowPwrEn = 0
 470 // bits[2] NbGateEn = 0
 471 // bits[3] NbCofChg = 0
 472 // bits[4] AltVidEn = 0
 473 // bits[7:5] ClkDivisor = 4
 474   {
 475     PciRegister,
 476     {
 477       AMD_FAMILY_10,                      // CpuFamily
 478       AMD_F10_C2                          // CpuRevision
 479     },
 480     {AMD_PF_SINGLE_CORE},                   // platformFeatures
 481     {{
 482       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
 483       0x80000000,                           // regData
 484       0xFF000000,                           // regMask
 485     }}
 486   },
 487 // F3x8C - NB Configuration High
 488 // Errata 373, bits[25] DisFastTprWr = 1
 489   {
 490     PciRegister,
 491     {
 492       AMD_FAMILY_10,                      // CpuFamily
 493       AMD_F10_ALL                         // CpuRevision
 494     },
 495     {AMD_PF_ALL},                           // platformFeatures
 496     {{
 497       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
 498       0x02000000,                           // regData
 499       0x02000000,                           // regMask
 500     }}
 501   },
 502 // F3x8C - NB Configuration High
 503 // Clear errata 373, bits[25] DisFastTprWr = 0
 504   {
 505     ProfileFixup,
 506     {
 507       AMD_FAMILY_10,                      // CpuFamily
 508       AMD_F10_ALL                         // CpuRevision
 509     },
 510     {AMD_PF_ALL},                           // platform Features
 511     {{
 512       PERFORMANCE_L3_CACHE,                 // Features
 513       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
 514       0x00000000,                           // regData
 515       0x02000000,                           // regMask
 516     }}
 517   },
 518 // F3xA0 - Power Control Miscellaneous
 519 // bits[13:11] PllLockTime = 1
 520   {
 521     PciRegister,
 522     {
 523       AMD_FAMILY_10,                      // CpuFamily
 524       AMD_F10_GT_C0                       // CpuRevision
 525     },
 526     {AMD_PF_ALL},                           // platformFeatures
 527     {{
 528       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
 529       0x00000800,                           // regData
 530       0x00003800,                           // regMask
 531     }}
 532   },
 533 // F3xA0 - Power Control Miscellaneous
 534 // bits[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
 535   {
 536     ProfileFixup,
 537     {
 538       AMD_FAMILY_10,                        // CpuFamily
 539       AMD_F10_C3                            // CpuRevision
 540     },
 541     {AMD_PF_ALL},                             // platformFeatures
 542     {{
 543       PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
 544       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
 545       0x00000200,                           // regData
 546       0x00000200,                           // regMask
 547     }}
 548   },
 549 // F3xA4 - Reported Temperature Control
 550 // bits[12:8] PerStepTimeDn = 15
 551 // bits[7] TmpSlewDnEn = 1
 552 // bits[6:5] TmpMaxDiffUp = 3
 553 // bits[4:0] PerStepTimeUp = 15
 554   {
 555     PciRegister,
 556     {
 557       AMD_FAMILY_10,                      // CpuFamily
 558       AMD_F10_ALL                         // CpuRevision
 559     },
 560     {AMD_PF_ALL},                           // platformFeatures
 561     {{
 562       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),  // Address
 563       0x00000FEF,                           // regData
 564       0x00001FFF,                           // regMask
 565     }}
 566   },
 567 // F3xD4 - Clock Power Timing Control 0
 568 // bits[11:8] ClkRampHystSel = 1
 569 // bits[30:28] NbClkDiv = 1
 570 // bits[31] NbClkDivApplyAll = 1
 571   {
 572     PciRegister,
 573     {
 574       AMD_FAMILY_10,                      // CpuFamily
 575       AMD_F10_ALL                         // CpuRevision
 576     },
 577     {AMD_PF_ALL},                           // platformFeatures
 578     {{
 579       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
 580       0xC0010F00,                           // regData
 581       0xF0030F00,                           // regMask
 582     }}
 583   },
 584 // F3xD8 - Clock Power Timing Control 1
 585 // bits[2:0] VSSlamTime = 6
 586 // bits[6:4] VSRampTime = 1
 587 // bits[26:24] ReConDel = 3
 588   {
 589     PciRegister,
 590     {
 591       AMD_FAMILY_10,                      // CpuFamily
 592       AMD_F10_ALL                         // CpuRevision
 593     },
 594     {AMD_PF_ALL},                           // platformFeatures
 595     {{
 596       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8),  // Address
 597       0x03000016,                           // regData
 598       0x0F000077,                           // regMask
 599     }}
 600   },
 601 // F3xDC - Clock Power Timing Control 2
 602 // bits[14:12] NbsynPtrAdj = 6
 603   {
 604     PciRegister,
 605     {
 606       AMD_FAMILY_10,                      // CpuFamily
 607       AMD_F10_ALL                         // CpuRevision
 608     },
 609     {AMD_PF_ALL},                           // platformFeatures
 610     {{
 611       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
 612       0x00006000,                           // regData
 613       0x00007000,                           // regMask
 614     }}
 615   },
 616 // F3xDC - Clock Power Timing Control 2
 617 // bits[18:16] CacheFlushOnHaltCtl = 0 to ensure AP cache stability at Early
 618   {
 619     PciRegister,
 620     {
 621       AMD_FAMILY_10,                      // CpuFamily
 622       AMD_F10_GT_Bx                       // CpuRevision
 623     },
 624     {AMD_PF_ALL},                           // platformFeatures
 625     {{
 626       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
 627       0x00000000,                           // regData
 628       0x00070000,                           // regMask
 629     }}
 630   },
 631 // F3x180 - NB Extended Configuration
 632 // bits[1] SyncFloodOnUsPwDataErr = 1
 633 // bits[5] DisPciCfgCpuMstAbtRsp = 1
 634 // bits[6] SyncFloodOnDatErr = 1
 635 // bits[7] SyncFloodOnTgtAbtErr = 1
 636 // bits[8] SyncOnProtEn = 1
 637 // bits[9] SyncOnUncNbAryEn = 1
 638 // bits[20] SyncFloodOnL3LeakErr = 1
 639 // bits[21] SyncFloodOnCpuLeakErr = 1
 640 // bits[22] SyncFloodOnTblWalkErr = 1
 641   {
 642     PciRegister,
 643     {
 644       AMD_FAMILY_10,                      // CpuFamily
 645       AMD_F10_ALL                         // CpuRevision
 646     },
 647     {AMD_PF_ALL},                           // platformFeatures
 648     {{
 649       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
 650       0x007003E2,                           // regData
 651       0x007003E2,                           // regMask
 652     }}
 653   },
 654 // F3x188 - NB Extended Configuration Low Register
 655 // bits[4] EnStpGntOnFlushMaskWakeup = 1
 656   {
 657     PciRegister,
 658     {
 659       AMD_FAMILY_10,                      // CpuFamily
 660       AMD_F10_C3                         // CpuRevision
 661     },
 662     {AMD_PF_ALL},                           // platformFeatures
 663     {{
 664       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
 665       0x00000010,                           // regData
 666       0x00000010,                           // regMask
 667     }}
 668   },
 669 // F3x1A0 - L3 Buffer Count Register
 670 // bits[14:12]  L3ToSriReqCBC = 4, 4 or fewer cores with L3 cache is 4.
 671   {
 672     CoreCountsPciRegister,
 673     {
 674       AMD_FAMILY_10,                      // CpuFamily
 675       AMD_F10_ALL                         // CpuRevision
 676     },
 677     {AMD_PF_ALL},                           // platformFeatures
 678     {{
 679       PERFORMANCE_L3_CACHE,
 680       (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores.
 681       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
 682       0x00004000,                               // regData
 683       0x00007000,                               // regMask
 684     }}
 685   },
 686 // F3x1A0 - L3 Buffer Count Register
 687 // bits[14:12]  L3ToSriReqCBC = 5, 5-core with L3 cache is 5.
 688   {
 689     CoreCountsPciRegister,
 690     {
 691       AMD_FAMILY_10,                      // CpuFamily
 692       AMD_F10_ALL                         // CpuRevision
 693     },
 694     {AMD_PF_ALL},                           // platformFeatures
 695     {{
 696       PERFORMANCE_L3_CACHE,
 697       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
 698       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
 699       0x00005000,                               // regData
 700       0x00007000,                               // regMask
 701     }}
 702   },
 703 // F3x1A0 - L3 Buffer Count Register
 704 // bits[14:12]  L3ToSriReqCBC = 6, 6-core with L3 cache is 6.
 705   {
 706     CoreCountsPciRegister,
 707     {
 708       AMD_FAMILY_10,                      // CpuFamily
 709       AMD_F10_ALL                         // CpuRevision
 710     },
 711     {AMD_PF_ALL},                           // platformFeatures
 712     {{
 713       PERFORMANCE_L3_CACHE,
 714       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
 715       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
 716       0x00006000,                               // regData
 717       0x00007000,                               // regMask
 718     }}
 719   },
 720 // F3x1B8 - L3 Control
 721 // bits[12] L3PrivReplEn = 1
 722   {
 723     PciRegister,
 724     {
 725       AMD_FAMILY_10,                      // CpuFamily
 726       AMD_F10_ALL                         // CpuRevision
 727     },
 728     {AMD_PF_ALL},                           // platformFeatures
 729     {{
 730       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
 731       0x00001000,                           // regData
 732       0x00001000,                           // regMask
 733     }}
 734   },
 735   // F4x1C4 - L3 Power Control Register
 736   // bits[8] L3PwrSavEn = 1
 737   {
 738     ProfileFixup,
 739     {
 740       AMD_FAMILY_10,                      // CpuFamily
 741       AMD_F10_ALL                         // CpuRevision
 742     },
 743     {AMD_PF_ALL},                           // platformFeatures
 744     {{
 745       PERFORMANCE_L3_CACHE,                 // Features
 746       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
 747       0x00000100,                           // regData
 748       0x00000100,                           // regMask
 749     }}
 750   },
 751 // F3x1CC - IBS Control
 752 // bits[8] LvtOffsetVal = 1
 753   {
 754     PciRegister,
 755     {
 756       AMD_FAMILY_10,                      // CpuFamily
 757       AMD_F10_GT_A2                       // CpuRevision
 758     },
 759     {AMD_PF_ALL},                           // platformFeatures
 760     {{
 761       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
 762       0x00000100,                           // regData
 763       0x00000100,                           // regMask
 764     }}
 765   }
 766 };
 767
 768 CONST REGISTER_TABLE ROMDATA F10PciRegisterTable = {
 769   PrimaryCores,
 770   (sizeof (F10PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
 771   F10PciRegisters,
 772 };