5 * AMD Family_10 CPB Initialization
7 * Enables core performance boost.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: CPU/F10
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
16 ******************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
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22 * modification, are permitted provided that the following conditions are met:
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24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
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43 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
52 #include "GeneralServices.h"
53 #include "cpuFamilyTranslation.h"
54 #include "cpuF10PowerMgmt.h"
55 #include "cpuFeatures.h"
56 #include "cpuRegisters.h"
57 #include "cpuF10Utilities.h"
63 #define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE
65 /*----------------------------------------------------------------------------------------
66 * D E F I N I T I O N S A N D M A C R O S
67 *----------------------------------------------------------------------------------------
70 /*----------------------------------------------------------------------------------------
71 * T Y P E D E F S A N D S T R U C T U R E S
72 *----------------------------------------------------------------------------------------
75 /*----------------------------------------------------------------------------------------
76 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
77 *----------------------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------------------
81 * E X P O R T E D F U N C T I O N S
82 *----------------------------------------------------------------------------------------
85 /*---------------------------------------------------------------------------------------*/
87 * BSC entry point for checking whether or not CPB is supported.
89 * @param[in] CpbServices The current CPU's family services.
90 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
91 * @param[in] Socket Zero based socket number to check.
92 * @param[in] StdHeader Config handle for library and services.
94 * @retval TRUE CPB is supported.
95 * @retval FALSE CPB is not supported.
101 IN CPB_FAMILY_SERVICES *CpbServices,
102 IN PLATFORM_CONFIGURATION *PlatformConfig,
104 IN AMD_CONFIG_PARAMS *StdHeader
107 UINT8 NumBoostStates;
109 NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
110 return (BOOLEAN) (NumBoostStates != 0);
114 /*---------------------------------------------------------------------------------------*/
116 * BSC entry point for for enabling Core Performance Boost.
118 * Set up F4x15C[BoostSrc] and start the PDMs according to the BKDG.
120 * @param[in] CpbServices The current CPU's family services.
121 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
122 * @param[in] EntryPoint Current CPU feature dispatch point.
123 * @param[in] Socket Zero based socket number to check.
124 * @param[in] StdHeader Config handle for library and services.
126 * @retval AGESA_SUCCESS Always succeeds.
132 IN CPB_FAMILY_SERVICES *CpbServices,
133 IN PLATFORM_CONFIGURATION *PlatformConfig,
134 IN UINT64 EntryPoint,
136 IN AMD_CONFIG_PARAMS *StdHeader
142 AGESA_STATUS IgnoredSts;
144 if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
145 for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
146 GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
147 PciAddress.Address.Function = FUNC_4;
148 PciAddress.Address.Register = CPB_CTRL_REG;
149 LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
150 ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 3;
151 IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
152 LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
154 PciAddress.Address.Function = FUNC_3;
155 PciAddress.Address.Register = POPUP_PSTATE_REG;
156 LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
157 ((POPUP_PSTATE_REGISTER *) (&CpbControl))->CacheFlushPopDownEn = 1;
158 LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
161 return AGESA_SUCCESS;
164 CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport =