5 * AMD Family_10 specific utility functions.
7 * Provides numerous utility functions specific to family 10h.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: CPU/F10
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
16 *****************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
53 #include "cpuRegisters.h"
54 #include "cpuServices.h"
55 #include "GeneralServices.h"
56 #include "cpuFamilyTranslation.h"
57 #include "cpuCommonF10Utilities.h"
62 #define FILECODE PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE
64 /*----------------------------------------------------------------------------------------
65 * D E F I N I T I O N S A N D M A C R O S
66 *----------------------------------------------------------------------------------------
69 /*----------------------------------------------------------------------------------------
70 * T Y P E D E F S A N D S T R U C T U R E S
71 *----------------------------------------------------------------------------------------
74 * Node ID MSR register fields.
75 * Provide the layout of fields in the Node ID MSR.
78 UINT64 NodeId:3; ///< The core is on the node with this node id.
79 UINT64 NodesPerProcessor:3; ///< The number of Nodes in this processor.
80 UINT64 HeapIndex:6; ///< The AP core heap index.
81 UINT64 :(63 - 11); ///< Reserved.
86 NODE_ID_MSR_FIELDS Fields; ///< Access the register as individual fields
87 UINT64 Value; ///< Access the register value.
90 /*----------------------------------------------------------------------------------------
91 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
92 *----------------------------------------------------------------------------------------
95 /*----------------------------------------------------------------------------------------
96 * E X P O R T E D F U N C T I O N S
97 *----------------------------------------------------------------------------------------
100 /*---------------------------------------------------------------------------------------*/
102 * Set warm reset status and count
104 * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
106 * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
108 * @param[in] FamilySpecificServices The current Family Specific Services.
109 * @param[in] StdHeader Handle of Header for calling lib functions and services.
110 * @param[in] Request Indicate warm reset status
114 F10SetAgesaWarmResetFlag (
115 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
116 IN AMD_CONFIG_PARAMS *StdHeader,
117 IN WARM_RESET_REQUEST *Request
123 PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
124 LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
126 // bit[5] - indicate a warm reset is or is not required
127 PciData &= ~(HT_INIT_BIOS_RST_DET_0);
128 PciData = PciData | (Request->RequestBit << 5);
130 // bit[10,9] - indicate warm reset status and count
131 PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
132 PciData |= Request->StateBits << 9;
134 LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
137 /*---------------------------------------------------------------------------------------*/
139 * Get warm reset status and count
141 * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
143 * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
145 * @param[in] FamilySpecificServices The current Family Specific Services.
146 * @param[in] StdHeader Config handle for library and services
147 * @param[out] Request Indicate warm reset status
151 F10GetAgesaWarmResetFlag (
152 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
153 IN AMD_CONFIG_PARAMS *StdHeader,
154 OUT WARM_RESET_REQUEST *Request
160 PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
161 LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
163 // bit[5] - indicate a warm reset is or is not required
164 Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
165 // bit[10,9] - indicate warm reset status and count
166 Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
169 /*---------------------------------------------------------------------------------------*/
171 * Use the Mailbox Register to get the Ap Mailbox info for the current core.
173 * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
175 * Access the mailbox register used with this NB family. This is valid until the
176 * point that some init code initializes the mailbox register for its normal use.
177 * The Machine Check Misc (Thresholding) register is available as both a PCI config
178 * register and a MSR, so it can be used as a mailbox from HT to other functions.
180 * @param[in] FamilySpecificServices The current Family Specific Services.
181 * @param[out] ApMailboxInfo The AP Mailbox info
182 * @param[in] StdHeader Handle of Header for calling lib functions and services.
186 F10GetApMailboxFromHardware (
187 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
188 OUT AP_MAILBOXES *ApMailboxInfo,
189 IN AMD_CONFIG_PARAMS *StdHeader
194 LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader);
195 // Mailbox info is in bits 32 thru 43, 12 bits.
196 ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
197 LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader);
198 // Mailbox info is in bits 32 thru 43, 12 bits.
199 ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
203 /*---------------------------------------------------------------------------------------*/
205 * Set the system AP core number in the AP's Mailbox.
207 * @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}.
209 * Access the mailbox register used with this NB family. This is only intended to
210 * run on the BSC at the time of initial AP launch.
212 * @param[in] FamilySpecificServices The current Family Specific Services.
213 * @param[in] Socket The AP's socket
214 * @param[in] Module The AP's module
215 * @param[in] ApCoreNumber The AP's unique core number
216 * @param[in] StdHeader Handle of Header for calling lib functions and services.
221 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
224 IN UINT32 ApCoreNumber,
225 IN AMD_CONFIG_PARAMS *StdHeader
228 UINT32 LocalPciRegister;
230 AGESA_STATUS IgnoredStatus;
232 GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus);
233 PciAddress.Address.Function = FUNC_3;
234 PciAddress.Address.Register = 0x170;
235 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
236 ((AP_MAIL_EXT_INFO *) &LocalPciRegister)->Fields.HeapIndex = ApCoreNumber;
237 LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
241 /*---------------------------------------------------------------------------------------*/
243 * Get this AP's system core number from hardware.
245 * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
247 * Returns the system core number from the scratch MSR, where
248 * it was saved at heap initialization.
250 * @param[in] FamilySpecificServices The current Family Specific Services.
251 * @param[in] StdHeader Handle of Header for calling lib functions and services.
253 * @return The AP's unique core number
257 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
258 IN AMD_CONFIG_PARAMS *StdHeader
261 NODE_ID_MSR NodeIdMsr;
263 LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader);
264 return (UINT32) NodeIdMsr.Fields.HeapIndex;
268 /*---------------------------------------------------------------------------------------*/
270 * Move the AP's core number from the mailbox to hardware.
272 * @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}.
274 * Transfers this AP's system core number from the mailbox to
275 * the NodeId MSR and initializes the other NodeId fields.
277 * @param[in] FamilySpecificServices The current Family Specific Services.
278 * @param[in] StdHeader Handle of Header for calling lib functions and services.
282 F10TransferApCoreNumber (
283 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
284 IN AMD_CONFIG_PARAMS *StdHeader
287 AP_MAILBOXES Mailboxes;
288 NODE_ID_MSR NodeIdMsr;
292 FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader);
293 NodeIdMsr.Fields.HeapIndex = Mailboxes.ApMailExtInfo.Fields.HeapIndex;
294 NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node;
295 NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType;
296 LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader);
298 // Indicate that the NodeId MSR is supported.
299 LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
300 ExtFeatures = (ExtFeatures | BIT51);
301 LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
305 /*---------------------------------------------------------------------------------------*/
307 * Return a number zero or one, based on the Core ID position in the initial APIC Id.
309 * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
311 * @param[in] FamilySpecificServices The current Family Specific Services.
312 * @param[in] StdHeader Handle of Header for calling lib functions and services.
314 * @retval CoreIdPositionZero Core Id is not low
315 * @retval CoreIdPositionOne Core Id is low
318 F10CpuAmdCoreIdPositionInInitialApicId (
319 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
320 IN AMD_CONFIG_PARAMS *StdHeader
323 UINT64 InitApicIdCpuIdLo;
325 // Check bit_54 [InitApicIdCpuIdLo] to find core id position.
326 LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
327 InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
328 return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);