src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 Rev E PCI tables with values as defined in BKDG
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/FAMILY/0x10/RevE
  10  * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "cpuRegisters.h"
  50 #include "Table.h"
  51 #include "Filecode.h"
  52 CODE_GROUP (G1_PEICC)
  53 RDATA_GROUP (G2_PEI)
  54
  55 #define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE
  56
  57 /*----------------------------------------------------------------------------------------
  58  *                   D E F I N I T I O N S    A N D    M A C R O S
  59  *----------------------------------------------------------------------------------------
  60  */
  61
  62 /*----------------------------------------------------------------------------------------
  63  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  64  *----------------------------------------------------------------------------------------
  65  */
  66
  67 /*----------------------------------------------------------------------------------------
  68  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  69  *----------------------------------------------------------------------------------------
  70  */
  71
  72 /*----------------------------------------------------------------------------------------
  73  *                          E X P O R T E D    F U N C T I O N S
  74  *----------------------------------------------------------------------------------------
  75  */
  76
  77 //  P C I    T a b l e s
  78 // ----------------------
  79
  80 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEPciRegisters[] =
  81 {
  82 // F0x68 -
  83 // BufRelPri for rev E
  84 // bits[14:13]  BufRelPri = 1
  85   {
  86     PciRegister,
  87     {
  88       AMD_FAMILY_10,                      // CpuFamily
  89       AMD_F10_Ex                          // CpuRevision
  90     },
  91     {AMD_PF_ALL},                           // platformFeatures
  92     {{
  93       MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68),   // Address
  94       0x00002000,                           // regData
  95       0x00006000,                           // regMask
  96     }}
  97   },
  98
  99 // F0x16C - Link Global Extended Control Register
 100 // bit[7:6] InLnSt = 0x01
 101   {
 102     PciRegister,
 103     {
 104       AMD_FAMILY_10,                      // CpuFamily
 105       AMD_F10_Ex                          // CpuRevision
 106     },
 107     {AMD_PF_SINGLE_LINK},                // platformFeatures
 108     {{
 109       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
 110       0x0000C026,                           // regData
 111       0x0000E03F,                           // regMask
 112     }}
 113   },
 114 // F0x16C - Link Global Extended Control Register
 115 // bit[15:13] ForceFullT0 = 6
 116 // bit[9] RXCalEn = 1
 117 // bit[5:0] T0Time = 0x26
 118   {
 119     PciRegister,
 120     {
 121       AMD_FAMILY_10,                      // CpuFamily
 122       AMD_F10_Ex                      // CpuRevision
 123     },
 124     {AMD_PF_SINGLE_LINK},                   // platformFeatures
 125     {{
 126       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
 127       0x0000C226,                           // regData
 128       0x0000E23F,                           // regMask
 129     }}
 130   },
 131 // F3x80 - ACPI Power State Control
 132 // ACPI State C2
 133 // bits[0] CpuPrbEn = 1
 134 // bits[1] NbLowPwrEn = 0
 135 // bits[2] NbGateEn = 0
 136 // bits[3] NbCofChg = 0
 137 // bits[4] AltVidEn = 0
 138 // bits[7:5] ClkDivisor = 1
 139 // ACPI State C3, C1E or Link init
 140 // bits[0] CpuPrbEn = 0
 141 // bits[1] NbLowPwrEn = 1
 142 // bits[2] NbGateEn = 1
 143 // bits[3] NbCofChg = 0
 144 // bits[4] AltVidEn = 0
 145 // bits[7:5] ClkDivisor = 7
 146   {
 147     PciRegister,
 148     {
 149       AMD_FAMILY_10,                      // CpuFamily
 150       AMD_F10_Ex                          // CpuRevision
 151     },
 152     {AMD_PF_ALL},                           // platformFeatures
 153     {{
 154       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 155       0x0000E681,                           // regData
 156       0x0000FFFF,                           // regMask
 157     }}
 158   },
 159 // F3xDC - Clock Power Timing Control 2
 160 // bits[14:12] NbsynPtrAdj = 6
 161   {
 162     PciRegister,
 163     {
 164       AMD_FAMILY_10,                      // CpuFamily
 165       AMD_F10_Ex                          // CpuRevision
 166     },
 167     {AMD_PF_ALL},                           // platformFeatures
 168     {{
 169       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
 170       0x00006000,                           // regData
 171       0x00007000,                           // regMask
 172     }}
 173   },
 174 // F3x1C4 - L3 Power Control Register
 175 // bits[8] L3PwrSavEn = 1
 176   {
 177     PciRegister,
 178     {
 179       AMD_FAMILY_10,                      // CpuFamily
 180       AMD_F10_Ex                          // CpuRevision
 181     },
 182     {AMD_PF_ALL},                           // platformFeatures
 183     {{
 184       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
 185       0x00000100,                           // regData
 186       0x00000100,                           // regMask
 187     }}
 188   },
 189 // F3x188 - NB Extended Configuration Low Register
 190 // bit[4] = EnStpGntOnFlushMaskWakeup
 191   {
 192     PciRegister,
 193     {
 194       AMD_FAMILY_10,                      // CpuFamily
 195       AMD_F10_Ex                          // CpuRevision
 196     },
 197     {AMD_PF_ALL},                           // platformFeatures
 198     {{
 199       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
 200       0x00000010,                           // regData
 201       0x00000010,                           // regMask
 202     }}
 203   },
 204 // F4x15C - Core Performance Boost Control
 205 // bits[1:0]   BoostSrc = 0
 206   {
 207     PciRegister,
 208     {
 209       AMD_FAMILY_10,                      // CpuFamily
 210       AMD_F10_Ex                          // CpuRevision
 211     },
 212     {AMD_PF_ALL},                           // platformFeatures
 213     {{
 214       MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
 215       0x00000000,                           // regData
 216       0x00000003,                           // regMask
 217     }}
 218   },
 219 };
 220
 221 CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable = {
 222   PrimaryCores,
 223   (sizeof (F10RevEPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
 224   F10RevEPciRegisters,
 225 };