5 * AMD Family_10 RevD Message-Based C1e feature support functions.
7 * Provides the functions necessary to initialize the message-based C1e feature.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: CPU/F10
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
16 ******************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
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32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
52 #include "cpuRegisters.h"
53 #include "cpuFamilyTranslation.h"
54 #include "cpuFeatures.h"
55 #include "cpuServices.h"
56 #include "GeneralServices.h"
57 #include "cpuMsgBasedC1e.h"
58 #include "cpuApicUtilities.h"
59 #include "cpuF10PowerMgmt.h"
60 #include "OptionMultiSocket.h"
65 #define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE
67 /*----------------------------------------------------------------------------------------
68 * D E F I N I T I O N S A N D M A C R O S
69 *----------------------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------------------
73 * T Y P E D E F S A N D S T R U C T U R E S
74 *----------------------------------------------------------------------------------------
77 /*----------------------------------------------------------------------------------------
78 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
79 *----------------------------------------------------------------------------------------
83 F10InitializeMsgBasedC1eOnCore (
84 IN VOID *BmStsAddress,
85 IN AMD_CONFIG_PARAMS *StdHeader
90 IsDramScrubberEnabled (
91 IN PCI_ADDR PciAddress,
92 IN AMD_CONFIG_PARAMS *StdHeader
95 /*----------------------------------------------------------------------------------------
96 * E X P O R T E D F U N C T I O N S
97 *----------------------------------------------------------------------------------------
99 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
100 /*---------------------------------------------------------------------------------------*/
102 * Should message-based C1e be enabled
104 * @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
105 * @param[in] Socket Processor socket to check.
106 * @param[in] StdHeader Config Handle for library, services.
108 * @retval TRUE HW C1e is supported.
113 F10IsMsgBasedC1eSupported (
114 IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
116 IN AMD_CONFIG_PARAMS *StdHeader
119 CPU_LOGICAL_ID LogicalId;
121 GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
122 return ((BOOLEAN) (((LogicalId.Revision) & AMD_F10_GT_D0) != 0));
125 /*---------------------------------------------------------------------------------------*/
127 * Core 0 task to enable message-based C1e on a family 10h CPU.
129 * @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
130 * @param[in] EntryPoint Timepoint designator.
131 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
132 * @param[in] StdHeader Config Handle for library, services.
134 * @return AGESA_SUCCESS Always succeeds.
139 F10InitializeMsgBasedC1e (
140 IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
141 IN UINT64 EntryPoint,
142 IN PLATFORM_CONFIGURATION *PlatformConfig,
143 IN AMD_CONFIG_PARAMS *StdHeader
150 UINT32 LocalPciRegister;
154 AGESA_STATUS IgnoredSts;
156 if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
157 // Note that this core 0 does NOT have the ability to launch
158 // any of its cores. Attempting to do so could lead to a system
161 // Set F3xA0[IdleExitEn] = 1
162 PciAddress.Address.Function = FUNC_3;
163 PciAddress.Address.Register = PW_CTL_MISC_REG;
164 AndMask = 0xFFFFFFFF;
166 ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
167 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
169 // Erratum #610, BIOS should set F3x1B8[5]
170 PciAddress.Address.Register = 0x1B8;
172 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x1B8
174 // Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
175 PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
177 ((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
178 OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
180 // Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
181 // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
182 ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
184 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
185 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
187 IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
189 for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
190 if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
191 PciAddress.Address.Function = FUNC_3;
192 PciAddress.Address.Register = CPTC0_REG;
193 if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
194 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
196 ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
198 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
199 LocalPciRegister &= AndMask;
200 LocalPciRegister |= OrMask;
201 LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
205 } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
206 // At early, this core 0 can launch its subordinate cores.
207 TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
208 TaskPtr.DataTransfer.DataSizeInDwords = 1;
209 TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
210 TaskPtr.DataTransfer.DataTransferFlags = 0;
211 TaskPtr.ExeFlags = WAIT_FOR_CORE;
212 ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
215 return AGESA_SUCCESS;
218 /*---------------------------------------------------------------------------------------*/
220 * Enable message-based C1e on a family 10h core.
222 * @param[in] BmStsAddress System I/O address of the bus master status bit.
223 * @param[in] StdHeader Config Handle for library, services.
228 F10InitializeMsgBasedC1eOnCore (
229 IN VOID *BmStsAddress,
230 IN AMD_CONFIG_PARAMS *StdHeader
233 UINT64 LocalMsrRegister;
235 // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
236 LibAmdMsrRead (MSR_INTPEND, &LocalMsrRegister, StdHeader);
237 ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
238 ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
239 ((INTPEND_MSR *) &LocalMsrRegister)->BmStsClrOnHltEn = 1;
240 ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsgDis = 0;
241 ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsg = 0;
242 ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
243 LibAmdMsrWrite (MSR_INTPEND, &LocalMsrRegister, StdHeader);
245 // Set MSRC001_0015[HltXSpCycEn] = 1
246 LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader);
247 LocalMsrRegister |= BIT12;
248 LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader);
251 /*---------------------------------------------------------------------------------------*/
253 * Check to see if the DRAM background scrubbers are enabled or not.
255 * @param[in] PciAddress Address of F10 socket/module to check.
256 * @param[in] StdHeader Config Handle for library, services.
258 * @retval TRUE Memory scrubbers are enabled on the current node.
259 * @retval FALSE Memory scrubbers are disabled on the current node.
263 IsDramScrubberEnabled (
264 IN PCI_ADDR PciAddress,
265 IN AMD_CONFIG_PARAMS *StdHeader
268 UINT32 LocalPciRegister;
270 PciAddress.Address.Function = FUNC_3;
271 PciAddress.Address.Register = 0x58;
272 LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
273 return ((BOOLEAN) ((LocalPciRegister & 0x1F) != 0));
277 CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e =
280 F10IsMsgBasedC1eSupported,
281 F10InitializeMsgBasedC1e