5 * AMD Family_10 BL PCI tables with values as defined in BKDG
7 * @xrefitem bom "File Content Label" "Release Content"
9 * @e sub-project: CPU/FAMILY/0x10
10 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
14 ******************************************************************************
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41 ******************************************************************************
44 /*----------------------------------------------------------------------------------------
45 * M O D U L E S U S E D
46 *----------------------------------------------------------------------------------------
49 #include "cpuRegisters.h"
51 #include "F10PackageType.h"
57 #define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
59 /*----------------------------------------------------------------------------------------
60 * D E F I N I T I O N S A N D M A C R O S
61 *----------------------------------------------------------------------------------------
64 /*----------------------------------------------------------------------------------------
65 * T Y P E D E F S A N D S T R U C T U R E S
66 *----------------------------------------------------------------------------------------
69 /*----------------------------------------------------------------------------------------
70 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
71 *----------------------------------------------------------------------------------------
74 /*----------------------------------------------------------------------------------------
75 * E X P O R T E D F U N C T I O N S
76 *----------------------------------------------------------------------------------------
80 // ----------------------
82 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
86 // F0x16C - Link Global Extended Control Register, Errata 351
87 // bit[15:13] ForceFullT0 = 0
88 // bit[5:0] T0Time = 0x14
92 AMD_FAMILY_10, // CpuFamily
93 AMD_F10_BL_C2 // CpuRevision
95 {AMD_PF_ALL}, // platformFeatures
97 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
98 0x00000014, // regData
99 0x0000E03F, // regMask
102 // F0x16C - Link Global Extended Control Register
103 // bit[7:6] InLnSt = 0x01
107 AMD_FAMILY_10, // CpuFamily
108 AMD_F10_BL_C3 // CpuRevision
110 {AMD_PF_SINGLE_LINK}, // platformFeatures
112 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
113 0x00000040, // regData
114 0x000000C0, // regMask
117 // F0x16C - Link Global Extended Control Register
118 // bit[15:13] ForceFullT0 = 6
119 // bit[9] RXCalEn = 1
120 // bit[5:0] T0Time = 0x26
124 AMD_FAMILY_10, // CpuFamily
125 AMD_F10_BL_C3 // CpuRevision
127 {AMD_PF_SINGLE_LINK}, // platformFeatures
129 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
130 0x0000C226, // regData
131 0x0000E23F, // regMask
134 // F0x170 - Link Extended Control Register - Link 0, sublink 0
135 // Errata 351 (only need to override single link case.)
140 AMD_FAMILY_10, // CpuFamily
141 AMD_F10_BL_C2 // CpuRevision
143 {AMD_PF_ALL}, // platformFeatures
145 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
146 0x00000000, // regData
147 0x00000100, // regMask
152 // F3x80 - ACPI Power State Control
153 // ACPI FIDVID Change
154 // bits[0] CpuPrbEn = 1
155 // bits[1] NbLowPwrEn = 1
156 // bits[2] NbGateEn = 0
157 // bits[3] NbCofChg = 1
158 // bits[4] AltVidEn = 0
159 // bits[7:5] ClkDivisor = 0
163 AMD_FAMILY_10, // CpuFamily
164 AMD_F10_BL_Cx // CpuRevision
166 {AMD_PF_SINGLE_LINK}, // platformFeatures
168 HT_HOST_FEATURES_ALL, // link feats
169 PACKAGE_TYPE_S1G3_S1G4, // package type
170 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
171 0x000B0000, // regData
172 0x00FF0000, // regMask
175 // F3xA0 - Power Control Miscellaneous
176 // bits[28] NbPstateForce = 1
180 AMD_FAMILY_10, // CpuFamily
181 AMD_F10_BL_C3 // CpuRevision
183 {AMD_PF_ALL}, // platformFeatures
185 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
186 0x10000000, // regData
187 0x10000000, // regMask
192 CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
194 (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),