5 * AMD Family_10 BL PCI tables with values as defined in BKDG
7 * @xrefitem bom "File Content Label" "Release Content"
9 * @e sub-project: CPU/FAMILY/0x10
10 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
14 ******************************************************************************
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41 ******************************************************************************
44 /*----------------------------------------------------------------------------------------
45 * M O D U L E S U S E D
46 *----------------------------------------------------------------------------------------
49 #include "cpuRegisters.h"
56 #define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
58 /*----------------------------------------------------------------------------------------
59 * D E F I N I T I O N S A N D M A C R O S
60 *----------------------------------------------------------------------------------------
63 /*----------------------------------------------------------------------------------------
64 * T Y P E D E F S A N D S T R U C T U R E S
65 *----------------------------------------------------------------------------------------
68 /*----------------------------------------------------------------------------------------
69 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
70 *----------------------------------------------------------------------------------------
73 /*----------------------------------------------------------------------------------------
74 * E X P O R T E D F U N C T I O N S
75 *----------------------------------------------------------------------------------------
79 // -------------------------
80 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
84 // NOTE: This entry is here for making this array not to be empty.
85 // This entry should be removed after adding another.
88 // Deemphasis Settings
91 // For BL-C3, also set [7]TxLs23ClkGateEn.
92 //deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
93 // No deemphasis 00h 00h 00h 0 0 0 0
94 // -3dB postcursor 12h 00h 00h 1 0 0 0
95 // -6dB postcursor 1Fh 00h 00h 1 0 0 0
96 // -8dB postcursor 1Fh 06h 00h 1 1 0 1
97 // -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
98 // -11dB postcursor with
99 // -8dB precursor 1Fh 06h 07h 1 1 1 1
104 AMD_FAMILY_10, // CpuFamily
105 AMD_F10_BL_C3 // CpuRevision
107 {AMD_PF_ALL}, // platformFeatures
109 DEEMPHASIS_LEVEL_NONE,
110 HTPHY_LINKTYPE_SL0_HT3, //
112 0x00000080, // regData
113 0xE01F1FDF, // regMask
118 CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
120 (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),