src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD CPU Cache Flush On Halt Function.
   6  *
   7  * Contains code to initialize Cache Flush On Halt feature for Family 10h BL.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  CPU/Family/0x10/BL
  12  * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
  13  *
  14  */
  15 /*
  16  ******************************************************************************
  17  *
  18  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  ******************************************************************************
  44  *----------------------------------------------------------------------------
  45  */
  46
  47
  48 /*
  49  *----------------------------------------------------------------------------
  50  *                                MODULES USED
  51  *
  52  *----------------------------------------------------------------------------
  53  */
  54 #include "AGESA.h"
  55 #include "cpuRegisters.h"
  56 #include "cpuServices.h"
  57 #include "cpuFamilyTranslation.h"
  58 #include "cpuPostInit.h"
  59 #include "cpuFeatures.h"
  60 #include "OptionMultiSocket.h"
  61 #include "Filecode.h"
  62 CODE_GROUP (G1_PEICC)
  63 RDATA_GROUP (G2_PEI)
  64 #define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
  65 /*----------------------------------------------------------------------------
  66  *                          DEFINITIONS AND MACROS
  67  *
  68  *----------------------------------------------------------------------------
  69  */
  70 extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
  71
  72 /*----------------------------------------------------------------------------
  73  *                           TYPEDEFS AND STRUCTURES
  74  *
  75  *----------------------------------------------------------------------------
  76  */
  77
  78 /*----------------------------------------------------------------------------------------
  79  *                          E X P O R T E D    F U N C T I O N S
  80  *----------------------------------------------------------------------------------------
  81  */
  82
  83 /*----------------------------------------------------------------------------
  84  *                        PROTOTYPES OF LOCAL FUNCTIONS
  85  *
  86  *----------------------------------------------------------------------------
  87  */
  88
  89 /*----------------------------------------------------------------------------------------
  90  *                          P U B L I C     F U N C T I O N S
  91  *----------------------------------------------------------------------------------------
  92  */
  93
  94 /* -----------------------------------------------------------------------------*/
  95 /**
  96  *    Enable BL-C Cpu Cache Flush On Halt Function
  97  *
  98  *    @param[in]       FamilySpecificServices   The current Family Specific Services.
  99  *    @param[in]       EntryPoint               Timepoint designator.
 100  *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
 101  *    @param[in]       StdHeader                Config Handle for library, services.
 102  */
 103 VOID
 104 SetF10BlCacheFlushOnHaltRegister (
 105   IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
 106   IN       UINT64                       EntryPoint,
 107   IN       PLATFORM_CONFIGURATION       *PlatformConfig,
 108   IN       AMD_CONFIG_PARAMS            *StdHeader
 109   )
 110 {
 111   UINT32       AndMask;
 112   UINT32       OrMask;
 113   UINT32       CoreCount;
 114   PCI_ADDR     PciAddress;
 115   CPU_LOGICAL_ID        CpuFamilyRevision;
 116
 117   if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
 118     GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
 119     PciAddress.Address.Function = FUNC_3;
 120     PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
 121     if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
 122       // F3xDC[25:19] = 04h
 123       // F3xDC[18:16] = 111b
 124       AndMask = 0xFC00FFFF;
 125       OrMask = 0x00270000;
 126     } else {
 127       // F3xDC[25:19] = 28h
 128       // F3xDC[18:16] = 111b
 129       AndMask = 0xFC00FFFF;
 130       OrMask = 0x01470000;
 131
 132       //For BL_C2 single Core, F3xDC[18:16] = 0
 133       GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
 134       if (CoreCount == 1) {
 135         if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
 136           OrMask = 0x01400000;
 137         }
 138       }
 139     }
 140
 141     // Get the Or Mask value from IDS
 142     IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
 143     OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3xDC
 144   }
 145 }
 146
 147 CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
 148 {
 149   0,
 150   SetF10BlCacheFlushOnHaltRegister
 151 };